Mercurial > vim
annotate runtime/ftplugin/systemverilog.vim @ 25773:11b656e74444
Update runtime files
Commit: https://github.com/vim/vim/commit/6c391a74fe90190796ca0b0c010112948a6e75d7
Author: Bram Moolenaar <Bram@vim.org>
Date: Thu Sep 9 21:55:11 2021 +0200
Update runtime files
| author | Bram Moolenaar <Bram@vim.org> |
|---|---|
| date | Thu, 09 Sep 2021 22:00:10 +0200 |
| parents | 840665e74421 |
| children |
| rev | line source |
|---|---|
|
5663
1dea14d4c738
Update runtime files. Add support for systemverilog.
Bram Moolenaar <bram@vim.org>
parents:
diff
changeset
|
1 " Vim filetype plugin file |
|
1dea14d4c738
Update runtime files. Add support for systemverilog.
Bram Moolenaar <bram@vim.org>
parents:
diff
changeset
|
2 " Language: SystemVerilog |
|
1dea14d4c738
Update runtime files. Add support for systemverilog.
Bram Moolenaar <bram@vim.org>
parents:
diff
changeset
|
3 " Maintainer: kocha <kocha.lsifrontend@gmail.com> |
| 24636 | 4 " Last Change: 07-May-2021 |
|
5663
1dea14d4c738
Update runtime files. Add support for systemverilog.
Bram Moolenaar <bram@vim.org>
parents:
diff
changeset
|
5 |
|
1dea14d4c738
Update runtime files. Add support for systemverilog.
Bram Moolenaar <bram@vim.org>
parents:
diff
changeset
|
6 if exists("b:did_ftplugin") |
|
1dea14d4c738
Update runtime files. Add support for systemverilog.
Bram Moolenaar <bram@vim.org>
parents:
diff
changeset
|
7 finish |
|
1dea14d4c738
Update runtime files. Add support for systemverilog.
Bram Moolenaar <bram@vim.org>
parents:
diff
changeset
|
8 endif |
|
1dea14d4c738
Update runtime files. Add support for systemverilog.
Bram Moolenaar <bram@vim.org>
parents:
diff
changeset
|
9 |
|
1dea14d4c738
Update runtime files. Add support for systemverilog.
Bram Moolenaar <bram@vim.org>
parents:
diff
changeset
|
10 " Behaves just like Verilog |
|
1dea14d4c738
Update runtime files. Add support for systemverilog.
Bram Moolenaar <bram@vim.org>
parents:
diff
changeset
|
11 runtime! ftplugin/verilog.vim |
| 24636 | 12 |
| 13 let s:cpo_save = &cpo | |
| 14 set cpo&vim | |
| 15 | |
| 16 " Add SystemVerilog keywords for matchit plugin. | |
| 17 if exists("loaded_matchit") | |
| 18 let b:match_words = | |
| 19 \ '\<begin\>:\<end\>,' . | |
| 20 \ '\<case\>\|\<casex\>\|\<casez\>:\<endcase\>,' . | |
| 21 \ '\<module\>:\<endmodule\>,' . | |
| 22 \ '\<if\>:`\@<!\<else\>,' . | |
| 23 \ '\<function\>:\<endfunction\>,' . | |
| 24 \ '`ifn\?def\>:`elsif\>:`else\>:`endif\>,' . | |
| 25 \ '\<task\>:\<endtask\>,' . | |
| 26 \ '\<specify\>:\<endspecify\>,' . | |
| 27 \ '\<config\>:\<endconfig\>,' . | |
| 28 \ '\<generate\>:\<endgenerate\>,' . | |
| 29 \ '\<fork\>:\<join\>\|\<join_any\>\|\<join_none\>,' . | |
| 30 \ '\<primitive\>:\<endprimitive\>,' . | |
| 31 \ '\<table\>:\<endtable\>,' . | |
| 32 \ '\<checker\>:\<endchecker\>,' . | |
| 33 \ '\<class\>:\<endclass\>,' . | |
| 34 \ '\<clocking\>:\<endclocking\>,' . | |
| 25773 | 35 \ '\<group\>:\<endgroup\>,' . |
| 24636 | 36 \ '\<interface\>:\<endinterface\>,' . |
| 37 \ '\<package\>:\<endpackage\>,' . | |
| 38 \ '\<program\>:\<endprogram\>,' . | |
| 39 \ '\<property\>:\<endproperty\>,' . | |
| 40 \ '\<sequence\>:\<endsequence\>' | |
| 41 endif | |
| 42 | |
| 43 let &cpo = s:cpo_save | |
| 44 unlet s:cpo_save |