comparison runtime/ftplugin/systemverilog.vim @ 24636:840665e74421

Update runtime files Commit: https://github.com/vim/vim/commit/3ec3217f0491e9ba8aa8ea02f7e454cd19a287ef Author: Bram Moolenaar <Bram@vim.org> Date: Sun May 16 12:39:47 2021 +0200 Update runtime files
author Bram Moolenaar <Bram@vim.org>
date Sun, 16 May 2021 12:45:04 +0200
parents 1dea14d4c738
children 11b656e74444
comparison
equal deleted inserted replaced
24635:d3bbbedec49b 24636:840665e74421
1 " Vim filetype plugin file 1 " Vim filetype plugin file
2 " Language: SystemVerilog 2 " Language: SystemVerilog
3 " Maintainer: kocha <kocha.lsifrontend@gmail.com> 3 " Maintainer: kocha <kocha.lsifrontend@gmail.com>
4 " Last Change: 12-Aug-2013. 4 " Last Change: 07-May-2021
5 5
6 if exists("b:did_ftplugin") 6 if exists("b:did_ftplugin")
7 finish 7 finish
8 endif 8 endif
9 9
10 " Behaves just like Verilog 10 " Behaves just like Verilog
11 runtime! ftplugin/verilog.vim 11 runtime! ftplugin/verilog.vim
12
13 let s:cpo_save = &cpo
14 set cpo&vim
15
16 " Add SystemVerilog keywords for matchit plugin.
17 if exists("loaded_matchit")
18 let b:match_words =
19 \ '\<begin\>:\<end\>,' .
20 \ '\<case\>\|\<casex\>\|\<casez\>:\<endcase\>,' .
21 \ '\<module\>:\<endmodule\>,' .
22 \ '\<if\>:`\@<!\<else\>,' .
23 \ '\<function\>:\<endfunction\>,' .
24 \ '`ifn\?def\>:`elsif\>:`else\>:`endif\>,' .
25 \ '\<task\>:\<endtask\>,' .
26 \ '\<specify\>:\<endspecify\>,' .
27 \ '\<config\>:\<endconfig\>,' .
28 \ '\<generate\>:\<endgenerate\>,' .
29 \ '\<fork\>:\<join\>\|\<join_any\>\|\<join_none\>,' .
30 \ '\<primitive\>:\<endprimitive\>,' .
31 \ '\<table\>:\<endtable\>,' .
32 \ '\<checker\>:\<endchecker\>,' .
33 \ '\<class\>:\<endclass\>,' .
34 \ '\<clocking\>:\<endclocking\>,' .
35 \ '\<gruop\>:\<endgruop\>,' .
36 \ '\<interface\>:\<endinterface\>,' .
37 \ '\<package\>:\<endpackage\>,' .
38 \ '\<program\>:\<endprogram\>,' .
39 \ '\<property\>:\<endproperty\>,' .
40 \ '\<sequence\>:\<endsequence\>'
41 endif
42
43 let &cpo = s:cpo_save
44 unlet s:cpo_save