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comparison runtime/indent/verilog.vim @ 11062:1218c5353e2b

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Runtime file updates. commit https://github.com/vim/vim/commit/214641f77df6f318a4b3a0b09723c19859a103f4 Author: Bram Moolenaar <Bram@vim.org> Date: Sun Mar 5 17:04:09 2017 +0100 Runtime file updates.
author Christian Brabandt <cb@256bit.org>
date Sun, 05 Mar 2017 17:15:05 +0100
parents 8b8ef1fed009
children 8d76a56861ec
comparison
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11061:0f11b92d7f5e 11062:1218c5353e2b
1 " Language: Verilog HDL 1 " Language: Verilog HDL
2 " Maintainer: Chih-Tsun Huang <cthuang@larc.ee.nthu.edu.tw> 2 " Maintainer: Chih-Tsun Huang <cthuang@cs.nthu.edu.tw>
3 " Last Change: 2011 Dec 10 by Thilo Six 3 " Last Change: 2017 Feb 24 by Chih-Tsun Huang
4 " URL: http://larc.ee.nthu.edu.tw/~cthuang/vim/indent/verilog.vim 4 " URL: http://www.cs.nthu.edu.tw/~cthuang/vim/indent/verilog.vim
5 " 5 "
6 " Credits: 6 " Credits:
7 " Suggestions for improvement, bug reports by 7 " Suggestions for improvement, bug reports by
8 " Takuya Fujiwara <tyru.exe@gmail.com>
9 " Thilo Six <debian@Xk2c.de>
8 " Leo Butlero <lbutler@brocade.com> 10 " Leo Butlero <lbutler@brocade.com>
9 " 11 "
10 " Buffer Variables: 12 " Buffer Variables:
11 " b:verilog_indent_modules : indenting after the declaration 13 " b:verilog_indent_modules : indenting after the declaration
12 " of module blocks 14 " of module blocks
36 function GetVerilogIndent() 38 function GetVerilogIndent()
37 39
38 if exists('b:verilog_indent_width') 40 if exists('b:verilog_indent_width')
39 let offset = b:verilog_indent_width 41 let offset = b:verilog_indent_width
40 else 42 else
41 let offset = &sw 43 let offset = shiftwidth()
42 endif 44 endif
43 if exists('b:verilog_indent_modules') 45 if exists('b:verilog_indent_modules')
44 let indent_modules = offset 46 let indent_modules = offset
45 else 47 else
46 let indent_modules = 0 48 let indent_modules = 0