Mercurial > vim

annotate runtime/syntax/vhdl.vim @ 31732:ef7a9a7eb197 v9.0.1198

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patch 9.0.1198: abstract class not supported yet Commit: https://github.com/vim/vim/commit/24a8d06d7f4db0865f374ced2f4d4b57cbc5b9e4 Author: Bram Moolenaar <Bram@vim.org> Date: Sat Jan 14 13:12:06 2023 +0000 patch 9.0.1198: abstract class not supported yet Problem: Abstract class not supported yet. Solution: Implement abstract class and add tests.
author Bram Moolenaar <Bram@vim.org>
date Sat, 14 Jan 2023 14:15:06 +0100
parents 1908e92b02fd
children
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1 " Vim syntax file
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2 " Language: VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language]
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3 " Maintainer: Daniel Kho <daniel.kho@logik.haus>
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4 " Previous Maintainer: Czo <Olivier.Sirol@lip6.fr>
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5 " Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
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6 " Last Changed: 2020 Apr 04 by Daniel Kho
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7
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8 " quit when a syntax file was already loaded
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9 if exists("b:current_syntax")
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10 finish
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11 endif
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12
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13 let s:cpo_save = &cpo
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14 set cpo&vim
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15
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16 " case is not significant
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17 syn case ignore
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18
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19 " VHDL 1076-2019 keywords
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20 syn keyword vhdlStatement access after alias all
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21 syn keyword vhdlStatement architecture array attribute
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22 syn keyword vhdlStatement assert assume
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23 syn keyword vhdlStatement begin block body buffer bus
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24 syn keyword vhdlStatement case component configuration constant
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25 syn keyword vhdlStatement context cover
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26 syn keyword vhdlStatement default disconnect downto
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27 syn keyword vhdlStatement elsif end entity exit
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28 syn keyword vhdlStatement file for function
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29 syn keyword vhdlStatement fairness force
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30 syn keyword vhdlStatement generate generic group guarded
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31 syn keyword vhdlStatement impure in inertial inout is
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32 syn keyword vhdlStatement label library linkage literal loop
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33 syn keyword vhdlStatement map
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34 syn keyword vhdlStatement new next null
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35 syn keyword vhdlStatement of on open others out
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36 syn keyword vhdlStatement package port postponed procedure process pure
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37 syn keyword vhdlStatement parameter property protected private
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38 syn keyword vhdlStatement range record register reject report return
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39 syn keyword vhdlStatement release restrict
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40 syn keyword vhdlStatement select severity signal shared subtype
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41 syn keyword vhdlStatement sequence strong
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42 syn keyword vhdlStatement then to transport type
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43 syn keyword vhdlStatement unaffected units until use
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44 syn keyword vhdlStatement variable view
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45 syn keyword vhdlStatement vpkg vmode vprop vunit
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46 syn keyword vhdlStatement wait when while with
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47
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48 " VHDL predefined severity levels
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49 syn keyword vhdlAttribute note warning error failure
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50
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51 " Linting of conditionals.
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52 syn match vhdlStatement "\<\(if\|else\)\>"
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53 syn match vhdlError "\<else\s\+if\>"
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54
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55 " Types and type qualifiers
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56 " Predefined standard VHDL types
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57 syn match vhdlType "\<bit\>\'\="
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58 syn match vhdlType "\<boolean\>\'\="
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59 syn match vhdlType "\<natural\>\'\="
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60 syn match vhdlType "\<positive\>\'\="
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61 syn match vhdlType "\<integer\>\'\="
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62 syn match vhdlType "\<real\>\'\="
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63 syn match vhdlType "\<time\>\'\="
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64
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65 syn match vhdlType "\<bit_vector\>\'\="
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66 syn match vhdlType "\<boolean_vector\>\'\="
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67 syn match vhdlType "\<integer_vector\>\'\="
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68 syn match vhdlType "\<real_vector\>\'\="
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69 syn match vhdlType "\<time_vector\>\'\="
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70
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71 syn match vhdlType "\<character\>\'\="
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72 syn match vhdlType "\<string\>\'\="
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73 syn keyword vhdlType line text side width
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74
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75 " Predefined standard IEEE VHDL types
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76 syn match vhdlType "\<std_ulogic\>\'\="
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77 syn match vhdlType "\<std_logic\>\'\="
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78 syn match vhdlType "\<std_ulogic_vector\>\'\="
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79 syn match vhdlType "\<std_logic_vector\>\'\="
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80 syn match vhdlType "\<unresolved_signed\>\'\="
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81 syn match vhdlType "\<unresolved_unsigned\>\'\="
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82 syn match vhdlType "\<u_signed\>\'\="
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83 syn match vhdlType "\<u_unsigned\>\'\="
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84 syn match vhdlType "\<signed\>\'\="
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85 syn match vhdlType "\<unsigned\>\'\="
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86
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88 " array attributes
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89 syn match vhdlAttribute "\'high"
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90 syn match vhdlAttribute "\'left"
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91 syn match vhdlAttribute "\'length"
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92 syn match vhdlAttribute "\'low"
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93 syn match vhdlAttribute "\'range"
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94 syn match vhdlAttribute "\'reverse_range"
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95 syn match vhdlAttribute "\'right"
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96 syn match vhdlAttribute "\'ascending"
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97 " block attributes
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98 syn match vhdlAttribute "\'simple_name"
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99 syn match vhdlAttribute "\'instance_name"
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100 syn match vhdlAttribute "\'path_name"
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101 syn match vhdlAttribute "\'foreign" " VHPI
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102 " signal attribute
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103 syn match vhdlAttribute "\'active"
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104 syn match vhdlAttribute "\'delayed"
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diff changeset
105 syn match vhdlAttribute "\'event"
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parents: 7183
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106 syn match vhdlAttribute "\'last_active"
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parents: 7183
diff changeset
107 syn match vhdlAttribute "\'last_event"
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parents: 7183
diff changeset
108 syn match vhdlAttribute "\'last_value"
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109 syn match vhdlAttribute "\'quiet"
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110 syn match vhdlAttribute "\'stable"
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parents: 7183
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111 syn match vhdlAttribute "\'transaction"
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parents: 7183
diff changeset
112 syn match vhdlAttribute "\'driving"
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113 syn match vhdlAttribute "\'driving_value"
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114 " type attributes
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115 syn match vhdlAttribute "\'base"
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parents: 7183
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116 syn match vhdlAttribute "\'subtype"
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parents: 7183
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117 syn match vhdlAttribute "\'element"
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parents: 7183
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118 syn match vhdlAttribute "\'leftof"
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119 syn match vhdlAttribute "\'pos"
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parents: 7183
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120 syn match vhdlAttribute "\'pred"
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121 syn match vhdlAttribute "\'rightof"
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122 syn match vhdlAttribute "\'succ"
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parents: 7183
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123 syn match vhdlAttribute "\'val"
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parents: 7183
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124 syn match vhdlAttribute "\'image"
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125 syn match vhdlAttribute "\'value"
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126 " VHDL-2019 interface attribute
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127 syn match vhdlAttribute "\'converse"
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128
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129 syn keyword vhdlBoolean true false
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130
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131 " for this vector values case is significant
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132 syn case match
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133 " Values for standard VHDL types
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134 syn match vhdlVector "\'[0L1HXWZU\-\?]\'"
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135 syn case ignore
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136
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137 syn match vhdlVector "B\"[01_]\+\""
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138 syn match vhdlVector "O\"[0-7_]\+\""
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parents: 7183
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139 syn match vhdlVector "X\"[0-9a-f_]\+\""
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parents: 7183
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140 syn match vhdlCharacter "'.'"
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141 syn region vhdlString start=+"+ end=+"+
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142
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143 " floating numbers
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144 syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>"
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parents: 7183
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145 syn match vhdlNumber "-\=\<\d\+\.\d\+\>"
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Christian Brabandt <cb@256bit.org>
parents: 7183
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146 syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\="
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Christian Brabandt <cb@256bit.org>
parents: 7183
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147 syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
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148 " integer numbers
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149 syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>"
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parents: 7183
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150 syn match vhdlNumber "-\=\<\d\+\>"
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parents: 7183
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151 syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\="
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parents: 7183
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152 syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
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153
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154 " operators
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155 syn keyword vhdlOperator and nand or nor xor xnor
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156 syn keyword vhdlOperator rol ror sla sll sra srl
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157 syn keyword vhdlOperator mod rem abs not
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158
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Christian Brabandt <cb@256bit.org>
parents: 6823
diff changeset
159 " Concatenation and math operators
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parents: 6823
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160 syn match vhdlOperator "&\|+\|-\|\*\|\/"
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161
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parents: 6823
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162 " Equality and comparison operators
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Christian Brabandt <cb@256bit.org>
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163 syn match vhdlOperator "=\|\/=\|>\|<\|>="
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164
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165 " Assignment operators
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166 syn match vhdlOperator "<=\|:="
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Christian Brabandt <cb@256bit.org>
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167 syn match vhdlOperator "=>"
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168
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169 " VHDL-202x concurrent signal association (spaceship) operator
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170 syn match vhdlOperator "<=>"
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171
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172 " VHDL-2008 conversion, matching equality/non-equality operators
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Christian Brabandt <cb@256bit.org>
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173 syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>="
30042ddff503 commit https://github.com/vim/vim/commit/60cce2fb736c8ff6fdb9603f502d3c15f1f7a25d
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174
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175 " VHDL-2008 external names
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176 syn match vhdlOperator "<<\|>>"
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177
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178 " Linting for illegal operators
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179 " '='
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180 syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+"
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181 syn match vhdlError "[=&+\-\*\\]\+\(=\)"
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182 " '>', '<'
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183 " Allow external names: '<< ... >>'
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184 syn match vhdlError "\(>\)[<&+\-\/\\]\+"
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185 syn match vhdlError "[&+\-\/\\]\+\(>\)"
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186 syn match vhdlError "\(<\)[&+\-\/\\]\+"
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187 syn match vhdlError "[>=&+\-\/\\]\+\(<\)"
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188 " Covers most operators
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189 " support negative sign after operators. E.g. q<=-b;
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190 " Supports VHDL-202x spaceship (concurrent simple signal association).
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Christian Brabandt <cb@256bit.org>
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191 syn match vhdlError "\(<=\)[<=&+\*\\?:]\+"
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Christian Brabandt <cb@256bit.org>
parents: 10051
diff changeset
192 syn match vhdlError "[>=&+\-\*\\:]\+\(=>\)"
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Christian Brabandt <cb@256bit.org>
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193 syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|:=\|=>\)[<>=&+\*\\?:]\+"
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194 syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\)"
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195 syn match vhdlError "\(?<\|?>\)[<>&+\*\/\\?:]\+"
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196 syn match vhdlError "\(<<\|>>\)[<>&+\*\/\\?:]\+"
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197
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198 "syn match vhdlError "[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)"
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199 " '/'
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200 syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+"
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parents: 6823
diff changeset
201 syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)"
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diff changeset
202
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Christian Brabandt <cb@256bit.org>
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203 syn match vhdlSpecial "<>"
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Christian Brabandt <cb@256bit.org>
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204 syn match vhdlSpecial "[().,;]"
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205
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206
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207 " time
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208 syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
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209 syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
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210
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211 syn case match
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212 syn keyword vhdlTodo contained TODO NOTE
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213 syn keyword vhdlFixme contained FIXME
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214 syn case ignore
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215
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216 syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell
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217 syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell
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218
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219 " Standard IEEE P1076.6 preprocessor directives (metacomments).
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220 syn match vhdlPreProc "/\*\s*rtl_synthesis\s\+\(on\|off\)\s*\*/"
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221 syn match vhdlPreProc "\(^\|\s\)--\s*rtl_synthesis\s\+\(on\|off\)\s*"
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222 syn match vhdlPreProc "/\*\s*rtl_syn\s\+\(on\|off\)\s*\*/"
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223 syn match vhdlPreProc "\(^\|\s\)--\s*rtl_syn\s\+\(on\|off\)\s*"
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224
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225 " Industry-standard directives. These are not standard VHDL, but are commonly
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226 " used in the industry.
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227 syn match vhdlPreProc "/\*\s*synthesis\s\+translate_\(on\|off\)\s*\*/"
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228 "syn match vhdlPreProc "/\*\s*simulation\s\+translate_\(on\|off\)\s*\*/"
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229 syn match vhdlPreProc "/\*\s*pragma\s\+translate_\(on\|off\)\s*\*/"
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230 syn match vhdlPreProc "/\*\s*pragma\s\+synthesis_\(on\|off\)\s*\*/"
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231 syn match vhdlPreProc "/\*\s*synopsys\s\+translate_\(on\|off\)\s*\*/"
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232
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233 syn match vhdlPreProc "\(^\|\s\)--\s*synthesis\s\+translate_\(on\|off\)\s*"
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234 "syn match vhdlPreProc "\(^\|\s\)--\s*simulation\s\+translate_\(on\|off\)\s*"
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235 syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+translate_\(on\|off\)\s*"
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236 syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+synthesis_\(on\|off\)\s*"
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237 syn match vhdlPreProc "\(^\|\s\)--\s*synopsys\s\+translate_\(on\|off\)\s*"
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238
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239 "Modify the following as needed. The trade-off is performance versus functionality.
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240 syn sync minlines=600
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241
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242 " Define the default highlighting.
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243 " Only when an item doesn't have highlighting yet
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244
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245 hi def link vhdlSpecial Special
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246 hi def link vhdlStatement Statement
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247 hi def link vhdlCharacter Character
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248 hi def link vhdlString String
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249 hi def link vhdlVector Number
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250 hi def link vhdlBoolean Number
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251 hi def link vhdlTodo Todo
46763b01cd9a commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
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252 hi def link vhdlFixme Fixme
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253 hi def link vhdlComment Comment
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254 hi def link vhdlNumber Number
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255 hi def link vhdlTime Number
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256 hi def link vhdlType Type
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257 hi def link vhdlOperator Operator
46763b01cd9a commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
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258 hi def link vhdlError Error
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259 hi def link vhdlAttribute Special
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260 hi def link vhdlPreProc PreProc
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261
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262
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263 let b:current_syntax = "vhdl"
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264
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265 let &cpo = s:cpo_save
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266 unlet s:cpo_save
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267
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268 " vim: ts=8