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annotate runtime/syntax/vhdl.vim @ 7176:30042ddff503

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commit https://github.com/vim/vim/commit/60cce2fb736c8ff6fdb9603f502d3c15f1f7a25d Author: Bram Moolenaar <Bram@vim.org> Date: Tue Oct 13 23:21:27 2015 +0200 Update runtime files.
author Christian Brabandt <cb@256bit.org>
date Tue, 13 Oct 2015 23:30:05 +0200
parents 0303182665d5
children ffad29dc7eee
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rev   line source
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1 " Vim syntax file
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2 " Language: VHDL
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3 " Maintainer: Daniel Kho <daniel.kho@tauhop.com>
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4 " Previous Maintainer: Czo <Olivier.Sirol@lip6.fr>
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5 " Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
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6 " Last Changed: 2015 Oct 13 by Daniel Kho
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7 " $Id: vhdl.vim,v 1.1 2004/06/13 15:34:56 vimboss Exp $
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8
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9 " VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
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10
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11 " For version 5.x: Clear all syntax items
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12 " For version 6.x: Quit when a syntax file was already loaded
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13 if version < 600
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14 syntax clear
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15 elseif exists("b:current_syntax")
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16 finish
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17 endif
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18
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19 let s:cpo_save = &cpo
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20 set cpo&vim
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21
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22 " This is not VHDL. I use the C-Preprocessor cpp to generate different binaries
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23 " from one VHDL source file. Unfortunately there is no preprocessor for VHDL
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24 " available. If you don't like this, please remove the following lines.
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25 "syn match cDefine "^#ifdef[ ]\+[A-Za-z_]\+"
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26 "syn match cDefine "^#endif"
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27
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28 " case is not significant
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29 syn case ignore
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30
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31 " VHDL keywords
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32 syn keyword vhdlStatement access after alias all assert
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33 syn keyword vhdlStatement architecture array attribute
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34 syn keyword vhdlStatement assume assume_guarantee
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35 syn keyword vhdlStatement begin block body buffer bus
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36 syn keyword vhdlStatement case component configuration constant
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37 syn keyword vhdlStatement context cover
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38 syn keyword vhdlStatement default disconnect downto
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39 syn keyword vhdlStatement elsif end entity exit
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40 syn keyword vhdlStatement file for function
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41 syn keyword vhdlStatement fairness force
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42 syn keyword vhdlStatement generate generic group guarded
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43 syn keyword vhdlStatement impure in inertial inout is
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44 syn keyword vhdlStatement label library linkage literal loop
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45 syn keyword vhdlStatement map
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46 syn keyword vhdlStatement new next null
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47 syn keyword vhdlStatement of on open others out
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48 syn keyword vhdlStatement package port postponed procedure process pure
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49 syn keyword vhdlStatement parameter property protected
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50 syn keyword vhdlStatement range record register reject report return
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51 syn keyword vhdlStatement release restrict restrict_guarantee
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52 syn keyword vhdlStatement select severity signal shared
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53 syn keyword vhdlStatement subtype
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54 syn keyword vhdlStatement sequence strong
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55 syn keyword vhdlStatement then to transport type
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56 syn keyword vhdlStatement unaffected units until use
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57 syn keyword vhdlStatement variable
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58 syn keyword vhdlStatement vmode vprop vunit
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59 syn keyword vhdlStatement wait when while with
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60 syn keyword vhdlStatement note warning error failure
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61
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62 " Special match for "if" and "else" since "else if" shouldn't be highlighted.
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63 " The right keyword is "elsif"
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64 syn match vhdlStatement "\<\(if\|else\)\>"
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65 syn match vhdlNone "\<else\s\+if\>$"
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66 syn match vhdlNone "\<else\s\+if\>\s"
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67
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68 " Predefined VHDL types
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69 syn keyword vhdlType bit bit_vector
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70 syn keyword vhdlType character boolean integer real time
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71 syn keyword vhdlType boolean_vector integer_vector real_vector time_vector
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72 syn keyword vhdlType string severity_level
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73 " Predefined standard ieee VHDL types
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74 syn keyword vhdlType positive natural signed unsigned
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75 syn keyword vhdlType unresolved_signed unresolved_unsigned u_signed u_unsigned
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76 syn keyword vhdlType line text
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77 syn keyword vhdlType std_logic std_logic_vector
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78 syn keyword vhdlType std_ulogic std_ulogic_vector
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79 " Predefined non standard VHDL types for Mentor Graphics Sys1076/QuickHDL
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80 "syn keyword vhdlType qsim_state qsim_state_vector
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81 "syn keyword vhdlType qsim_12state qsim_12state_vector
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82 "syn keyword vhdlType qsim_strength
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83 " Predefined non standard VHDL types for Alliance VLSI CAD
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84 "syn keyword vhdlType mux_bit mux_vector reg_bit reg_vector wor_bit wor_vector
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85
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86 " array attributes
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87 syn match vhdlAttribute "\'high"
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88 syn match vhdlAttribute "\'left"
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89 syn match vhdlAttribute "\'length"
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90 syn match vhdlAttribute "\'low"
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91 syn match vhdlAttribute "\'range"
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92 syn match vhdlAttribute "\'reverse_range"
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93 syn match vhdlAttribute "\'right"
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94 syn match vhdlAttribute "\'ascending"
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95 " block attributes
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96 "syn match vhdlAttribute "\'behaviour" " Non-standard VHDL
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97 "syn match vhdlAttribute "\'structure" " Non-standard VHDL
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98 syn match vhdlAttribute "\'simple_name"
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99 syn match vhdlAttribute "\'instance_name"
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100 syn match vhdlAttribute "\'path_name"
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101 syn match vhdlAttribute "\'foreign" " VHPI
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102 " signal attribute
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103 syn match vhdlAttribute "\'active"
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104 syn match vhdlAttribute "\'delayed"
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105 syn match vhdlAttribute "\'event"
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106 syn match vhdlAttribute "\'last_active"
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107 syn match vhdlAttribute "\'last_event"
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108 syn match vhdlAttribute "\'last_value"
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109 syn match vhdlAttribute "\'quiet"
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110 syn match vhdlAttribute "\'stable"
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111 syn match vhdlAttribute "\'transaction"
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112 syn match vhdlAttribute "\'driving"
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113 syn match vhdlAttribute "\'driving_value"
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114 " type attributes
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115 syn match vhdlAttribute "\'base"
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116 syn match vhdlAttribute "\'subtype"
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117 syn match vhdlAttribute "\'element"
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118 syn match vhdlAttribute "\'leftof"
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119 syn match vhdlAttribute "\'pos"
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120 syn match vhdlAttribute "\'pred"
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121 syn match vhdlAttribute "\'rightof"
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122 syn match vhdlAttribute "\'succ"
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123 syn match vhdlAttribute "\'val"
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124 syn match vhdlAttribute "\'image"
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125 syn match vhdlAttribute "\'value"
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126
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127 syn keyword vhdlBoolean true false
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128
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129 " for this vector values case is significant
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130 syn case match
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131 " Values for standard VHDL types
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132 syn match vhdlVector "\'[0L1HXWZU\-\?]\'"
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133 " Values for non standard VHDL types qsim_12state for Mentor Graphics Sys1076/QuickHDL
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134 "syn keyword vhdlVector S0S S1S SXS S0R S1R SXR S0Z S1Z SXZ S0I S1I SXI
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135 syn case ignore
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136
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137 syn match vhdlVector "B\"[01_]\+\""
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138 syn match vhdlVector "O\"[0-7_]\+\""
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139 syn match vhdlVector "X\"[0-9a-f_]\+\""
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140 syn match vhdlCharacter "'.'"
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141 syn region vhdlString start=+"+ end=+"+
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142
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143 " floating numbers
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144 syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>"
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145 syn match vhdlNumber "-\=\<\d\+\.\d\+\>"
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146 syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\="
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147 syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
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148 " integer numbers
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149 syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>"
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150 syn match vhdlNumber "-\=\<\d\+\>"
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151 syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\="
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152 syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
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153
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154 " operators
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155 syn keyword vhdlOperator and nand or nor xor xnor
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156 syn keyword vhdlOperator rol ror sla sll sra srl
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157 syn keyword vhdlOperator mod rem abs not
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158 " TODO remove the following line. You can't have a sequence of */=+ as an operator for example.
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159 "syn match vhdlOperator "[&><=:+\-*\/|]"
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160 " The following lines match valid and invalid operators.
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161
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162 " Concatenation and math operators
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163 syn match vhdlOperator "&\|+\|-\|\*\|\/"
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164
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165 " Equality and comparison operators
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166 syn match vhdlOperator "=\|\/=\|>\|<\|>="
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167
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168 " Assignment operators
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169 syn match vhdlOperator "<=\|:="
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170 syn match vhdlOperator "=>"
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171
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172 " VHDL-2008 conversion, matching equality/non-equality operators
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173 syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>="
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174
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175 " Linting for illegal operators
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176 " '='
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177 syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+"
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178 syn match vhdlError "[=&+\-\*\\]\+\(=\)"
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179 " '>', '<'
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180 syn match vhdlError "\(>\)[<>&+\-\/\\]\+"
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181 syn match vhdlError "[>&+\-\/\\]\+\(>\)"
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182 syn match vhdlError "\(<\)[<&+\-\/\\]\+"
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183 syn match vhdlError "[<>=&+\-\/\\]\+\(<\)"
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184 " Covers most operators
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185 syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|<=\|:=\|=>\)[<>=&+\-\*\\?:]\+"
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186 syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\|=>\)"
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187 syn match vhdlError "\(?<\|?>\)[<>&+\-\*\/\\?:]\+"
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188
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189 "syn match vhdlError "[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)"
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190 " '/'
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191 syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+"
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192 syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)"
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193
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194 syn match vhdlSpecial "<>"
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195 syn match vhdlSpecial "[().,;]"
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196
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197
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198 " time
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199 syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
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200 syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
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201
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202 syn case match
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203 syn keyword vhdlTodo contained TODO NOTE
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204 syn keyword vhdlFixme contained FIXME
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205 syn case ignore
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206
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207 syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell
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208 syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell
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209
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210 " Industry-standard directives. These are not standard VHDL, but are commonly
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211 " used in the industry.
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212 syn match vhdlPreProc "/\* synthesis .* \*/"
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213 "syn match vhdlPreProc "/\* simulation .* \*/"
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214 syn match vhdlPreProc "/\* pragma .* \*/"
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215 syn match vhdlPreProc "/\* synopsys .* \*/"
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216 syn match vhdlPreProc "--\s*synthesis .*"
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217 "syn match vhdlPreProc "--\s*simulation .*"
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218 syn match vhdlPreProc "--\s*pragma .*"
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219 syn match vhdlPreProc "--\s*synopsys .*"
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220
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221 "Modify the following as needed. The trade-off is performance versus functionality.
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222 syn sync minlines=600
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223
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224 " Define the default highlighting.
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225 " For version 5.7 and earlier: only when not done already
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226 " For version 5.8 and later: only when an item doesn't have highlighting yet
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227 if version >= 508 || !exists("did_vhdl_syntax_inits")
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228 if version < 508
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229 let did_vhdl_syntax_inits = 1
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230 command -nargs=+ HiLink hi link <args>
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231 else
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232 command -nargs=+ HiLink hi def link <args>
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233 endif
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234
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235 HiLink vhdlSpecial Special
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236 HiLink vhdlStatement Statement
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237 HiLink vhdlCharacter Character
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238 HiLink vhdlString String
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239 HiLink vhdlVector Number
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240 HiLink vhdlBoolean Number
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241 HiLink vhdlTodo Todo
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242 HiLink vhdlFixme Fixme
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243 HiLink vhdlComment Comment
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244 HiLink vhdlNumber Number
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245 HiLink vhdlTime Number
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246 HiLink vhdlType Type
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247 HiLink vhdlOperator Operator
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248 HiLink vhdlError Error
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249 HiLink vhdlAttribute Special
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250 HiLink vhdlPreProc PreProc
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251
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252 delcommand HiLink
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253 endif
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254
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255 let b:current_syntax = "vhdl"
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256
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257 let &cpo = s:cpo_save
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258 unlet s:cpo_save
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259 " vim: ts=8