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annotate runtime/syntax/vhdl.vim @ 7687:61354fabf8a2 v7.4.1142

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commit https://github.com/vim/vim/commit/b8060fe862f684b591f9ac679eac5b2594d6c5a0 Author: Bram Moolenaar <Bram@vim.org> Date: Tue Jan 19 22:29:28 2016 +0100 patch 7.4.1142 Problem: Cannot define keyword characters for a syntax file. Solution: Add the ":syn iskeyword" command. (Christian Brabandt)
author Christian Brabandt <cb@256bit.org>
date Tue, 19 Jan 2016 22:30:07 +0100
parents 444efa5f5015
children 4c6ad81d41fe
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rev   line source
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1 " Vim syntax file
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2 " Language: VHDL
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3 " Maintainer: Daniel Kho <daniel.kho@tauhop.com>
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4 " Previous Maintainer: Czo <Olivier.Sirol@lip6.fr>
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5 " Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
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6 " Last Changed: 2015 Dec 4 by Daniel Kho
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7
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8 " VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
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9
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10 " For version 5.x: Clear all syntax items
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11 " For version 6.x: Quit when a syntax file was already loaded
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12 if version < 600
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13 syntax clear
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14 elseif exists("b:current_syntax")
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15 finish
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16 endif
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17
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18 let s:cpo_save = &cpo
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19 set cpo&vim
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20
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21 " case is not significant
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22 syn case ignore
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23
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24 " VHDL keywords
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25 syn keyword vhdlStatement access after alias all assert
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26 syn keyword vhdlStatement architecture array attribute
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27 syn keyword vhdlStatement assume assume_guarantee
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28 syn keyword vhdlStatement begin block body buffer bus
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29 syn keyword vhdlStatement case component configuration constant
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30 syn keyword vhdlStatement context cover
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31 syn keyword vhdlStatement default disconnect downto
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32 syn keyword vhdlStatement elsif end entity exit
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33 syn keyword vhdlStatement file for function
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34 syn keyword vhdlStatement fairness force
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35 syn keyword vhdlStatement generate generic group guarded
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36 syn keyword vhdlStatement impure in inertial inout is
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37 syn keyword vhdlStatement label library linkage literal loop
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38 syn keyword vhdlStatement map
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39 syn keyword vhdlStatement new next null
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40 syn keyword vhdlStatement of on open others out
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41 syn keyword vhdlStatement package port postponed procedure process pure
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42 syn keyword vhdlStatement parameter property protected
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43 syn keyword vhdlStatement range record register reject report return
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44 syn keyword vhdlStatement release restrict restrict_guarantee
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45 syn keyword vhdlStatement select severity signal shared
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46 syn keyword vhdlStatement subtype
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47 syn keyword vhdlStatement sequence strong
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48 syn keyword vhdlStatement then to transport type
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49 syn keyword vhdlStatement unaffected units until use
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50 syn keyword vhdlStatement variable
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51 syn keyword vhdlStatement vmode vprop vunit
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52 syn keyword vhdlStatement wait when while with
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53 syn keyword vhdlStatement note warning error failure
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54
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55 " Linting of conditionals.
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56 syn match vhdlStatement "\<\(if\|else\)\>"
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57 syn match vhdlError "\<else\s\+if\>"
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58
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59 " Predefined VHDL types
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60 syn keyword vhdlType bit bit_vector
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61 syn keyword vhdlType character boolean integer real time
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62 syn keyword vhdlType boolean_vector integer_vector real_vector time_vector
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63 syn keyword vhdlType string severity_level
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64 " Predefined standard ieee VHDL types
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65 syn keyword vhdlType positive natural signed unsigned
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66 syn keyword vhdlType unresolved_signed unresolved_unsigned u_signed u_unsigned
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67 syn keyword vhdlType line text
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68 syn keyword vhdlType std_logic std_logic_vector
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69 syn keyword vhdlType std_ulogic std_ulogic_vector
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71 " array attributes
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72 syn match vhdlAttribute "\'high"
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73 syn match vhdlAttribute "\'left"
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74 syn match vhdlAttribute "\'length"
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75 syn match vhdlAttribute "\'low"
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76 syn match vhdlAttribute "\'range"
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77 syn match vhdlAttribute "\'reverse_range"
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78 syn match vhdlAttribute "\'right"
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79 syn match vhdlAttribute "\'ascending"
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80 " block attributes
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81 syn match vhdlAttribute "\'simple_name"
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82 syn match vhdlAttribute "\'instance_name"
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83 syn match vhdlAttribute "\'path_name"
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84 syn match vhdlAttribute "\'foreign" " VHPI
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85 " signal attribute
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86 syn match vhdlAttribute "\'active"
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87 syn match vhdlAttribute "\'delayed"
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88 syn match vhdlAttribute "\'event"
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89 syn match vhdlAttribute "\'last_active"
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90 syn match vhdlAttribute "\'last_event"
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91 syn match vhdlAttribute "\'last_value"
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92 syn match vhdlAttribute "\'quiet"
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93 syn match vhdlAttribute "\'stable"
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94 syn match vhdlAttribute "\'transaction"
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95 syn match vhdlAttribute "\'driving"
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96 syn match vhdlAttribute "\'driving_value"
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97 " type attributes
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98 syn match vhdlAttribute "\'base"
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99 syn match vhdlAttribute "\'subtype"
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100 syn match vhdlAttribute "\'element"
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101 syn match vhdlAttribute "\'leftof"
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102 syn match vhdlAttribute "\'pos"
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103 syn match vhdlAttribute "\'pred"
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104 syn match vhdlAttribute "\'rightof"
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105 syn match vhdlAttribute "\'succ"
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106 syn match vhdlAttribute "\'val"
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107 syn match vhdlAttribute "\'image"
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108 syn match vhdlAttribute "\'value"
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109
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110 syn keyword vhdlBoolean true false
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111
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112 " for this vector values case is significant
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113 syn case match
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114 " Values for standard VHDL types
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115 syn match vhdlVector "\'[0L1HXWZU\-\?]\'"
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116 syn case ignore
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117
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118 syn match vhdlVector "B\"[01_]\+\""
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119 syn match vhdlVector "O\"[0-7_]\+\""
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120 syn match vhdlVector "X\"[0-9a-f_]\+\""
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121 syn match vhdlCharacter "'.'"
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122 syn region vhdlString start=+"+ end=+"+
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123
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124 " floating numbers
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125 syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>"
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126 syn match vhdlNumber "-\=\<\d\+\.\d\+\>"
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127 syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\="
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128 syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
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129 " integer numbers
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130 syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>"
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131 syn match vhdlNumber "-\=\<\d\+\>"
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132 syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\="
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133 syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\="
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134
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135 " operators
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136 syn keyword vhdlOperator and nand or nor xor xnor
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137 syn keyword vhdlOperator rol ror sla sll sra srl
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138 syn keyword vhdlOperator mod rem abs not
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139
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140 " Concatenation and math operators
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141 syn match vhdlOperator "&\|+\|-\|\*\|\/"
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142
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143 " Equality and comparison operators
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144 syn match vhdlOperator "=\|\/=\|>\|<\|>="
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145
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146 " Assignment operators
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147 syn match vhdlOperator "<=\|:="
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148 syn match vhdlOperator "=>"
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149
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150 " VHDL-2008 conversion, matching equality/non-equality operators
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151 syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>="
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152
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153 " VHDL-2008 external names
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154 syn match vhdlOperator "<<\|>>"
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155
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156 " Linting for illegal operators
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157 " '='
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158 syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+"
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159 syn match vhdlError "[=&+\-\*\\]\+\(=\)"
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160 " '>', '<'
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161 " Allow external names: '<< ... >>'
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162 syn match vhdlError "\(>\)[<&+\-\/\\]\+"
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163 syn match vhdlError "[&+\-\/\\]\+\(>\)"
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164 syn match vhdlError "\(<\)[&+\-\/\\]\+"
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165 syn match vhdlError "[>=&+\-\/\\]\+\(<\)"
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166 " Covers most operators
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167 " support negative sign after operators. E.g. q<=-b;
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168 syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|<=\|:=\|=>\)[<>=&+\*\\?:]\+"
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169 syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\|=>\)"
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170 syn match vhdlError "\(?<\|?>\)[<>&+\*\/\\?:]\+"
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171 syn match vhdlError "\(<<\|>>\)[<>&+\*\/\\?:]\+"
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172
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173 "syn match vhdlError "[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)"
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174 " '/'
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175 syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+"
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176 syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)"
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177
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178 syn match vhdlSpecial "<>"
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179 syn match vhdlSpecial "[().,;]"
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180
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181
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182 " time
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183 syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
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184 syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
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185
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186 syn case match
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187 syn keyword vhdlTodo contained TODO NOTE
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188 syn keyword vhdlFixme contained FIXME
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189 syn case ignore
5362
ab1508486b12 Update runtime files. Add support for J.
Bram Moolenaar <bram@vim.org>
parents: 3557
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190
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191 syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell
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192 syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell
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193
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194 " Industry-standard directives. These are not standard VHDL, but are commonly
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195 " used in the industry.
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196 syn match vhdlPreProc "/\*\s*synthesis\s\+translate_\(on\|off\)\s*\*/"
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197 "syn match vhdlPreProc "/\*\s*simulation\s\+translate_\(on\|off\)\s*\*/"
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198 syn match vhdlPreProc "/\*\s*pragma\s\+synthesis_\(on\|off\)\s*\*/"
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199 syn match vhdlPreProc "/\*\s*synopsys\s\+translate_\(on\|off\)\s*\*/"
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200
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201 syn match vhdlPreProc "\(^\|\s\)--\s*synthesis\s\+translate_\(on\|off\)\s*"
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202 "syn match vhdlPreProc "\(^\|\s\)--\s*simulation\s\+translate_\(on\|off\)\s*"
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203 syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+synthesis_\(on\|off\)\s*"
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204 syn match vhdlPreProc "\(^\|\s\)--\s*synopsys\s\+translate_\(on\|off\)\s*"
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205
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206 "Modify the following as needed. The trade-off is performance versus functionality.
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207 syn sync minlines=600
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208
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209 " Define the default highlighting.
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210 " For version 5.7 and earlier: only when not done already
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211 " For version 5.8 and later: only when an item doesn't have highlighting yet
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212 if version >= 508 || !exists("did_vhdl_syntax_inits")
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213 if version < 508
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214 let did_vhdl_syntax_inits = 1
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215 command -nargs=+ HiLink hi link <args>
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216 else
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217 command -nargs=+ HiLink hi def link <args>
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218 endif
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219
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220 HiLink vhdlSpecial Special
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221 HiLink vhdlStatement Statement
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222 HiLink vhdlCharacter Character
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223 HiLink vhdlString String
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224 HiLink vhdlVector Number
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225 HiLink vhdlBoolean Number
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226 HiLink vhdlTodo Todo
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227 HiLink vhdlFixme Fixme
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228 HiLink vhdlComment Comment
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229 HiLink vhdlNumber Number
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230 HiLink vhdlTime Number
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231 HiLink vhdlType Type
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232 HiLink vhdlOperator Operator
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233 HiLink vhdlError Error
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234 HiLink vhdlAttribute Special
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235 HiLink vhdlPreProc PreProc
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236
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237 delcommand HiLink
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238 endif
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239
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240 let b:current_syntax = "vhdl"
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241
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242 let &cpo = s:cpo_save
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243 unlet s:cpo_save
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244 " vim: ts=8