view runtime/ftplugin/systemverilog.vim @ 33363:14b9adfe6822 v9.0.1943

patch 9.0.1943: CI not run with clang-17 Commit: https://github.com/vim/vim/commit/f109bf93c9402e4e3122a7ae7846e6feae4fa222 Author: Philip H <47042125+pheiduck@users.noreply.github.com> Date: Mon Sep 25 21:05:00 2023 +0200 patch 9.0.1943: CI not run with clang-17 Problem: CI not run with clang-17 Solution: Update CI to use clang-17 closes: #12745 Signed-off-by: Christian Brabandt <cb@256bit.org> Co-authored-by: Philip H <47042125+pheiduck@users.noreply.github.com>
author Christian Brabandt <cb@256bit.org>
date Mon, 25 Sep 2023 21:15:08 +0200
parents 11b656e74444
children
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" Vim filetype plugin file
" Language:    SystemVerilog
" Maintainer:  kocha <kocha.lsifrontend@gmail.com>
" Last Change: 07-May-2021

if exists("b:did_ftplugin")
  finish
endif

" Behaves just like Verilog
runtime! ftplugin/verilog.vim

let s:cpo_save = &cpo
set cpo&vim

" Add SystemVerilog keywords for matchit plugin.
if exists("loaded_matchit")
  let b:match_words =
    \ '\<begin\>:\<end\>,' .
    \ '\<case\>\|\<casex\>\|\<casez\>:\<endcase\>,' .
    \ '\<module\>:\<endmodule\>,' .
    \ '\<if\>:`\@<!\<else\>,' .
    \ '\<function\>:\<endfunction\>,' .
    \ '`ifn\?def\>:`elsif\>:`else\>:`endif\>,' .
    \ '\<task\>:\<endtask\>,' .
    \ '\<specify\>:\<endspecify\>,' .
    \ '\<config\>:\<endconfig\>,' .
    \ '\<generate\>:\<endgenerate\>,' .
    \ '\<fork\>:\<join\>\|\<join_any\>\|\<join_none\>,' .
    \ '\<primitive\>:\<endprimitive\>,' .
    \ '\<table\>:\<endtable\>,' .
    \ '\<checker\>:\<endchecker\>,' .
    \ '\<class\>:\<endclass\>,' .
    \ '\<clocking\>:\<endclocking\>,' .
    \ '\<group\>:\<endgroup\>,' .
    \ '\<interface\>:\<endinterface\>,' .
    \ '\<package\>:\<endpackage\>,' .
    \ '\<program\>:\<endprogram\>,' .
    \ '\<property\>:\<endproperty\>,' .
    \ '\<sequence\>:\<endsequence\>'
endif

let &cpo = s:cpo_save
unlet s:cpo_save