Mercurial > vim
view runtime/syntax/verilog.vim @ 33083:79b2eb83f2df v9.0.1827
patch 9.0.1827: xxd: no color support
Commit: https://github.com/vim/vim/commit/e2528ae11134cdf35c312754b124aba4963d8054
Author: Aapo Rantalainen <aapo.rantalainen@gmail.com>
Date: Thu Aug 31 17:58:13 2023 +0200
patch 9.0.1827: xxd: no color support
Problem: xxd: no color support
Solution: Add color support using xxd -R
Add some basic color support for xxd
The hex-value and value are both colored with the same color depending
on the hex-value, e.g.:
0x00 = white
0xff = blue
printable = green
non-printable = red
tabs and linebreaks = yellow
Each character needs 11 more bytes to contain color. (Same color in a
row could contain only one overhead but the logic how xxd creates colums
must be then changed.) Size of colored output is increased by factor of
~6. Also grepping the output will break when colors is used.
Flag for color is "-R", because less uses "-R".
Color uses parameters auto,always,never same as less and grep (among
others).
E.g.
xxd -R always $FILE | less -R
Add some screen-tests (that currently on work on linux) to verify the
feature works as expected.
closes: #12131
Signed-off-by: Christian Brabandt <cb@256bit.org>
Co-authored-by: Aapo Rantalainen <aapo.rantalainen@gmail.com>
author | Christian Brabandt <cb@256bit.org> |
---|---|
date | Thu, 31 Aug 2023 18:15:03 +0200 |
parents | 46763b01cd9a |
children |
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" Vim syntax file " Language: Verilog " Maintainer: Mun Johl <Mun.Johl@emulex.com> " Last Update: Wed Jul 20 16:04:19 PDT 2011 " quit when a syntax file was already loaded if exists("b:current_syntax") finish endif " Set the local value of the 'iskeyword' option. " NOTE: '?' was added so that verilogNumber would be processed correctly when " '?' is the last character of the number. setlocal iskeyword=@,48-57,63,_,192-255 " A bunch of useful Verilog keywords syn keyword verilogStatement always and assign automatic buf syn keyword verilogStatement bufif0 bufif1 cell cmos syn keyword verilogStatement config deassign defparam design syn keyword verilogStatement disable edge endconfig syn keyword verilogStatement endfunction endgenerate endmodule syn keyword verilogStatement endprimitive endspecify endtable endtask syn keyword verilogStatement event force function syn keyword verilogStatement generate genvar highz0 highz1 ifnone syn keyword verilogStatement incdir include initial inout input syn keyword verilogStatement instance integer large liblist syn keyword verilogStatement library localparam macromodule medium syn keyword verilogStatement module nand negedge nmos nor syn keyword verilogStatement noshowcancelled not notif0 notif1 or syn keyword verilogStatement output parameter pmos posedge primitive syn keyword verilogStatement pull0 pull1 pulldown pullup syn keyword verilogStatement pulsestyle_onevent pulsestyle_ondetect syn keyword verilogStatement rcmos real realtime reg release syn keyword verilogStatement rnmos rpmos rtran rtranif0 rtranif1 syn keyword verilogStatement scalared showcancelled signed small syn keyword verilogStatement specify specparam strong0 strong1 syn keyword verilogStatement supply0 supply1 table task time tran syn keyword verilogStatement tranif0 tranif1 tri tri0 tri1 triand syn keyword verilogStatement trior trireg unsigned use vectored wait syn keyword verilogStatement wand weak0 weak1 wire wor xnor xor syn keyword verilogLabel begin end fork join syn keyword verilogConditional if else case casex casez default endcase syn keyword verilogRepeat forever repeat while for syn keyword verilogTodo contained TODO FIXME syn match verilogOperator "[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]" syn region verilogComment start="/\*" end="\*/" contains=verilogTodo,@Spell syn match verilogComment "//.*" contains=verilogTodo,@Spell "syn match verilogGlobal "`[a-zA-Z0-9_]\+\>" syn match verilogGlobal "`celldefine" syn match verilogGlobal "`default_nettype" syn match verilogGlobal "`define" syn match verilogGlobal "`else" syn match verilogGlobal "`elsif" syn match verilogGlobal "`endcelldefine" syn match verilogGlobal "`endif" syn match verilogGlobal "`ifdef" syn match verilogGlobal "`ifndef" syn match verilogGlobal "`include" syn match verilogGlobal "`line" syn match verilogGlobal "`nounconnected_drive" syn match verilogGlobal "`resetall" syn match verilogGlobal "`timescale" syn match verilogGlobal "`unconnected_drive" syn match verilogGlobal "`undef" syn match verilogGlobal "$[a-zA-Z0-9_]\+\>" syn match verilogConstant "\<[A-Z][A-Z0-9_]\+\>" syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[bB]\s*[0-1_xXzZ?]\+\>" syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[oO]\s*[0-7_xXzZ?]\+\>" syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[dD]\s*[0-9_xXzZ?]\+\>" syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[hH]\s*[0-9a-fA-F_xXzZ?]\+\>" syn match verilogNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)\>" syn region verilogString start=+"+ skip=+\\"+ end=+"+ contains=verilogEscape,@Spell syn match verilogEscape +\\[nt"\\]+ contained syn match verilogEscape "\\\o\o\=\o\=" contained " Directives syn match verilogDirective "//\s*synopsys\>.*$" syn region verilogDirective start="/\*\s*synopsys\>" end="\*/" syn region verilogDirective start="//\s*synopsys dc_script_begin\>" end="//\s*synopsys dc_script_end\>" syn match verilogDirective "//\s*\$s\>.*$" syn region verilogDirective start="/\*\s*\$s\>" end="\*/" syn region verilogDirective start="//\s*\$s dc_script_begin\>" end="//\s*\$s dc_script_end\>" "Modify the following as needed. The trade-off is performance versus "functionality. syn sync minlines=50 " Define the default highlighting. " Only when an item doesn't have highlighting yet " The default highlighting. hi def link verilogCharacter Character hi def link verilogConditional Conditional hi def link verilogRepeat Repeat hi def link verilogString String hi def link verilogTodo Todo hi def link verilogComment Comment hi def link verilogConstant Constant hi def link verilogLabel Label hi def link verilogNumber Number hi def link verilogOperator Special hi def link verilogStatement Statement hi def link verilogGlobal Define hi def link verilogDirective SpecialComment hi def link verilogEscape Special let b:current_syntax = "verilog" " vim: ts=8