Mercurial > vim
annotate runtime/syntax/verilogams.vim @ 33230:d64e4106dd91 v9.0.1889
patch 9.0.1889: Vim9 static tests fail
Commit: https://github.com/vim/vim/commit/0405405536f06a3bf384757be4affa9c1a07bdcd
Author: Yegappan Lakshmanan <yegappan@yahoo.com>
Date: Sun Sep 10 18:12:56 2023 +0200
patch 9.0.1889: Vim9 static tests fail
Problem: Vim9 static tests fail
Solution: Fix tests, make CI happy ;)
closes: #13064
Signed-off-by: Christian Brabandt <cb@256bit.org>
Co-authored-by: Yegappan Lakshmanan <yegappan@yahoo.com>
author | Christian Brabandt <cb@256bit.org> |
---|---|
date | Sun, 10 Sep 2023 18:15:05 +0200 |
parents | 46763b01cd9a |
children |
rev | line source |
---|---|
481 | 1 " Vim syntax file |
1621 | 2 " Language: Verilog-AMS |
3 " Maintainer: S. Myles Prather <smprather@gmail.com> | |
4 " | |
5 " Version 1.1 S. Myles Prather <smprather@gmail.com> | |
6 " Moved some keywords to the type category. | |
7 " Added the metrix suffixes to the number matcher. | |
8 " Version 1.2 Prasanna Tamhankar <pratam@gmail.com> | |
9 " Minor reserved keyword updates. | |
10 " Last Update: Thursday September 15 15:36:03 CST 2005 | |
481 | 11 |
10048
43efa4f5a8ea
commit https://github.com/vim/vim/commit/89bcfda6834aba724d12554a34b9ed49f5789fd5
Christian Brabandt <cb@256bit.org>
parents:
1621
diff
changeset
|
12 " quit when a syntax file was already loaded |
43efa4f5a8ea
commit https://github.com/vim/vim/commit/89bcfda6834aba724d12554a34b9ed49f5789fd5
Christian Brabandt <cb@256bit.org>
parents:
1621
diff
changeset
|
13 if exists("b:current_syntax") |
481 | 14 finish |
15 endif | |
16 | |
17 " Set the local value of the 'iskeyword' option | |
10048
43efa4f5a8ea
commit https://github.com/vim/vim/commit/89bcfda6834aba724d12554a34b9ed49f5789fd5
Christian Brabandt <cb@256bit.org>
parents:
1621
diff
changeset
|
18 setlocal iskeyword=@,48-57,_,192-255 |
481 | 19 |
20 " Annex B.1 'All keywords' | |
21 syn keyword verilogamsStatement above abs absdelay acos acosh ac_stim | |
22 syn keyword verilogamsStatement always analog analysis and asin | |
1621 | 23 syn keyword verilogamsStatement asinh assign atan atan2 atanh |
24 syn keyword verilogamsStatement buf bufif0 bufif1 ceil cmos connectmodule | |
481 | 25 syn keyword verilogamsStatement connectrules cos cosh cross ddt ddx deassign |
26 syn keyword verilogamsStatement defparam disable discipline | |
27 syn keyword verilogamsStatement driver_update edge enddiscipline | |
1621 | 28 syn keyword verilogamsStatement endconnectrules endmodule endfunction endgenerate |
481 | 29 syn keyword verilogamsStatement endnature endparamset endprimitive endspecify |
30 syn keyword verilogamsStatement endtable endtask event exp final_step | |
31 syn keyword verilogamsStatement flicker_noise floor flow force fork | |
1621 | 32 syn keyword verilogamsStatement function generate highz0 |
33 syn keyword verilogamsStatement highz1 hypot idt idtmod if ifnone inf initial | |
481 | 34 syn keyword verilogamsStatement initial_step inout input join |
35 syn keyword verilogamsStatement laplace_nd laplace_np laplace_zd laplace_zp | |
36 syn keyword verilogamsStatement large last_crossing limexp ln localparam log | |
37 syn keyword verilogamsStatement macromodule max medium min module nand nature | |
38 syn keyword verilogamsStatement negedge net_resolution nmos noise_table nor not | |
39 syn keyword verilogamsStatement notif0 notif1 or output paramset pmos | |
40 syn keyword verilogamsType parameter real integer electrical input output | |
41 syn keyword verilogamsType inout reg tri tri0 tri1 triand trior trireg | |
1621 | 42 syn keyword verilogamsType string from exclude aliasparam ground genvar |
43 syn keyword verilogamsType branch time realtime | |
481 | 44 syn keyword verilogamsStatement posedge potential pow primitive pull0 pull1 |
45 syn keyword verilogamsStatement pullup pulldown rcmos release | |
46 syn keyword verilogamsStatement rnmos rpmos rtran rtranif0 rtranif1 | |
47 syn keyword verilogamsStatement scalared sin sinh slew small specify specparam | |
48 syn keyword verilogamsStatement sqrt strong0 strong1 supply0 supply1 | |
1621 | 49 syn keyword verilogamsStatement table tan tanh task timer tran tranif0 |
481 | 50 syn keyword verilogamsStatement tranif1 transition |
51 syn keyword verilogamsStatement vectored wait wand weak0 weak1 | |
52 syn keyword verilogamsStatement white_noise wire wor wreal xnor xor zi_nd | |
1621 | 53 syn keyword verilogamsStatement zi_np zi_zd zi_zp |
481 | 54 syn keyword verilogamsRepeat forever repeat while for |
55 syn keyword verilogamsLabel begin end | |
56 syn keyword verilogamsConditional if else case casex casez default endcase | |
57 syn match verilogamsConstant ":inf"lc=1 | |
58 syn match verilogamsConstant "-inf"lc=1 | |
59 " Annex B.2 Discipline/nature | |
60 syn keyword verilogamsStatement abstol access continuous ddt_nature discrete | |
61 syn keyword verilogamsStatement domain idt_nature units | |
62 " Annex B.3 Connect Rules | |
63 syn keyword verilogamsStatement connect merged resolveto split | |
64 | |
65 syn match verilogamsOperator "[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]" | |
66 syn match verilogamsOperator "<+" | |
67 syn match verilogamsStatement "[vV]("me=e-1 | |
68 syn match verilogamsStatement "[iI]("me=e-1 | |
69 | |
70 syn keyword verilogamsTodo contained TODO | |
71 syn region verilogamsComment start="/\*" end="\*/" contains=verilogamsTodo | |
72 syn match verilogamsComment "//.*" contains=verilogamsTodo | |
73 | |
74 syn match verilogamsGlobal "`celldefine" | |
75 syn match verilogamsGlobal "`default_nettype" | |
76 syn match verilogamsGlobal "`define" | |
77 syn match verilogamsGlobal "`else" | |
78 syn match verilogamsGlobal "`elsif" | |
79 syn match verilogamsGlobal "`endcelldefine" | |
80 syn match verilogamsGlobal "`endif" | |
81 syn match verilogamsGlobal "`ifdef" | |
82 syn match verilogamsGlobal "`ifndef" | |
83 syn match verilogamsGlobal "`include" | |
84 syn match verilogamsGlobal "`line" | |
85 syn match verilogamsGlobal "`nounconnected_drive" | |
86 syn match verilogamsGlobal "`resetall" | |
87 syn match verilogamsGlobal "`timescale" | |
88 syn match verilogamsGlobal "`unconnected_drive" | |
89 syn match verilogamsGlobal "`undef" | |
90 syn match verilogamsSystask "$[a-zA-Z0-9_]\+\>" | |
91 | |
92 syn match verilogamsConstant "\<[A-Z][A-Z0-9_]\+\>" | |
93 | |
94 syn match verilogamsNumber "\(\<\d\+\|\)'[bB]\s*[0-1_xXzZ?]\+\>" | |
95 syn match verilogamsNumber "\(\<\d\+\|\)'[oO]\s*[0-7_xXzZ?]\+\>" | |
96 syn match verilogamsNumber "\(\<\d\+\|\)'[dD]\s*[0-9_xXzZ?]\+\>" | |
97 syn match verilogamsNumber "\(\<\d\+\|\)'[hH]\s*[0-9a-fA-F_xXzZ?]\+\>" | |
1621 | 98 syn match verilogamsNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)[TGMKkmunpfa]\=\>" |
481 | 99 |
100 syn region verilogamsString start=+"+ skip=+\\"+ end=+"+ contains=verilogamsEscape | |
101 syn match verilogamsEscape +\\[nt"\\]+ contained | |
102 syn match verilogamsEscape "\\\o\o\=\o\=" contained | |
103 | |
104 "Modify the following as needed. The trade-off is performance versus | |
105 "functionality. | |
106 syn sync lines=50 | |
107 | |
108 " Define the default highlighting. | |
10048
43efa4f5a8ea
commit https://github.com/vim/vim/commit/89bcfda6834aba724d12554a34b9ed49f5789fd5
Christian Brabandt <cb@256bit.org>
parents:
1621
diff
changeset
|
109 " Only when an item doesn't have highlighting yet |
481 | 110 |
10048
43efa4f5a8ea
commit https://github.com/vim/vim/commit/89bcfda6834aba724d12554a34b9ed49f5789fd5
Christian Brabandt <cb@256bit.org>
parents:
1621
diff
changeset
|
111 " The default highlighting. |
10051
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
112 hi def link verilogamsCharacter Character |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
113 hi def link verilogamsConditional Conditional |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
114 hi def link verilogamsRepeat Repeat |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
115 hi def link verilogamsString String |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
116 hi def link verilogamsTodo Todo |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
117 hi def link verilogamsComment Comment |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
118 hi def link verilogamsConstant Constant |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
119 hi def link verilogamsLabel Label |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
120 hi def link verilogamsNumber Number |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
121 hi def link verilogamsOperator Special |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
122 hi def link verilogamsStatement Statement |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
123 hi def link verilogamsGlobal Define |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
124 hi def link verilogamsDirective SpecialComment |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
125 hi def link verilogamsEscape Special |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
126 hi def link verilogamsType Type |
46763b01cd9a
commit https://github.com/vim/vim/commit/f37506f60f87d52a9e8850e30067645e2b13783c
Christian Brabandt <cb@256bit.org>
parents:
10048
diff
changeset
|
127 hi def link verilogamsSystask Function |
481 | 128 |
129 | |
130 let b:current_syntax = "verilogams" | |
131 | |
132 " vim: ts=8 |