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annotate runtime/syntax/systemverilog.vim @ 8686:92657771648f v7.4.1632

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commit https://github.com/vim/vim/commit/6098957458e538682f54e23de217da06200876a3 Author: Bram Moolenaar <Bram@vim.org> Date: Mon Mar 21 22:38:34 2016 +0100 patch 7.4.1632 Problem: List of test targets is outdated. Solution: Update to current list of test targets.
author Christian Brabandt <cb@256bit.org>
date Mon, 21 Mar 2016 22:45:05 +0100
parents 1dea14d4c738
children 43efa4f5a8ea
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 " Vim syntax file
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2 " Language: SystemVerilog
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3 " Maintainer: kocha <kocha.lsifrontend@gmail.com>
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4 " Last Change: 12-Aug-2013.
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5
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6 " For version 5.x: Clear all syntax items
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7 " For version 6.x: Quit when a syntax file was already loaded
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8 if version < 600
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9 syntax clear
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10 elseif exists("b:current_syntax")
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11 finish
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12 endif
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13
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14 " Read in Verilog syntax files
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15 if version < 600
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16 so <sfile>:p:h/verilog.vim
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17 else
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18 runtime! syntax/verilog.vim
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19 unlet b:current_syntax
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20 endif
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21
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22 " IEEE1800-2005
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23 syn keyword systemverilogStatement always_comb always_ff always_latch
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24 syn keyword systemverilogStatement class endclass new
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25 syn keyword systemverilogStatement virtual local const protected
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26 syn keyword systemverilogStatement package endpackage
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27 syn keyword systemverilogStatement rand randc constraint randomize
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28 syn keyword systemverilogStatement with inside dist
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29 syn keyword systemverilogStatement sequence endsequence randsequence
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30 syn keyword systemverilogStatement srandom
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31 syn keyword systemverilogStatement logic bit byte
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32 syn keyword systemverilogStatement int longint shortint
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33 syn keyword systemverilogStatement struct packed
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34 syn keyword systemverilogStatement final
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35 syn keyword systemverilogStatement import export
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36 syn keyword systemverilogStatement context pure
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37 syn keyword systemverilogStatement void shortreal chandle string
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38 syn keyword systemverilogStatement clocking endclocking iff
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39 syn keyword systemverilogStatement interface endinterface modport
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40 syn keyword systemverilogStatement cover covergroup coverpoint endgroup
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41 syn keyword systemverilogStatement property endproperty
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42 syn keyword systemverilogStatement program endprogram
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43 syn keyword systemverilogStatement bins binsof illegal_bins ignore_bins
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44 syn keyword systemverilogStatement alias matches solve static assert
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45 syn keyword systemverilogStatement assume super before expect bind
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46 syn keyword systemverilogStatement extends null tagged extern this
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47 syn keyword systemverilogStatement first_match throughout timeprecision
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48 syn keyword systemverilogStatement timeunit type union
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49 syn keyword systemverilogStatement uwire var cross ref wait_order intersect
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50 syn keyword systemverilogStatement wildcard within
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51
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52 syn keyword systemverilogTypeDef typedef enum
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53
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54 syn keyword systemverilogConditional randcase
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55 syn keyword systemverilogConditional unique priority
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56
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57 syn keyword systemverilogRepeat return break continue
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58 syn keyword systemverilogRepeat do foreach
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59
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60 syn keyword systemverilogLabel join_any join_none forkjoin
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61
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62 " IEEE1800-2009 add
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63 syn keyword systemverilogStatement checker endchecker
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64 syn keyword systemverilogStatement accept_on reject_on
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65 syn keyword systemverilogStatement sync_accept_on sync_reject_on
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66 syn keyword systemverilogStatement eventually nexttime until until_with
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67 syn keyword systemverilogStatement s_always s_eventually s_nexttime s_until s_until_with
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68 syn keyword systemverilogStatement let untyped
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69 syn keyword systemverilogStatement strong weak
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70 syn keyword systemverilogStatement restrict global implies
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71
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72 syn keyword systemverilogConditional unique0
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73
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74 " IEEE1800-2012 add
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75 syn keyword systemverilogStatement implements
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76 syn keyword systemverilogStatement interconnect soft nettype
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77
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78 " Define the default highlighting.
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79 if version >= 508 || !exists("did_systemverilog_syn_inits")
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80 if version < 508
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81 let did_systemverilog_syn_inits = 1
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82 command -nargs=+ HiLink hi link <args>
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83 else
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84 command -nargs=+ HiLink hi def link <args>
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85 endif
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86
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87 " The default highlighting.
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88 HiLink systemverilogStatement Statement
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89 HiLink systemverilogTypeDef TypeDef
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90 HiLink systemverilogConditional Conditional
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91 HiLink systemverilogRepeat Repeat
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92 HiLink systemverilogLabel Label
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93 HiLink systemverilogGlobal Define
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94 HiLink systemverilogNumber Number
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95
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96 delcommand HiLink
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97 endif
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98
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99 let b:current_syntax = "systemverilog"
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100
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101 " vim: ts=8