Mercurial > vim
annotate runtime/syntax/vhdl.vim @ 6999:dc1b678f0e4e v7.4.817
patch 7.4.817
Problem: Invalid memory access in file_pat_to_reg_pat().
Solution: Use vim_isspace() instead of checking for a space only. (Dominique
Pelle)
| author | Bram Moolenaar <bram@vim.org> |
|---|---|
| date | Tue, 11 Aug 2015 16:20:05 +0200 |
| parents | 0303182665d5 |
| children | 30042ddff503 |
| rev | line source |
|---|---|
| 7 | 1 " Vim syntax file |
| 2 " Language: VHDL | |
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3 " Maintainer: Daniel Kho <daniel.kho@tauhop.com> |
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ab1508486b12
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4 " Previous Maintainer: Czo <Olivier.Sirol@lip6.fr> |
| 7 | 5 " Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn> |
| 6823 | 6 " Last Changed: 2015 Apr 25 by Daniel Kho |
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7 " $Id: vhdl.vim,v 1.1 2004/06/13 15:34:56 vimboss Exp $ |
| 7 | 8 |
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9 " VHSIC (Very High Speed Integrated Circuit) Hardware Description Language |
| 7 | 10 |
| 11 " For version 5.x: Clear all syntax items | |
| 12 " For version 6.x: Quit when a syntax file was already loaded | |
| 13 if version < 600 | |
| 14 syntax clear | |
| 15 elseif exists("b:current_syntax") | |
| 16 finish | |
| 17 endif | |
| 18 | |
| 3312 | 19 let s:cpo_save = &cpo |
| 20 set cpo&vim | |
| 21 | |
| 7 | 22 " This is not VHDL. I use the C-Preprocessor cpp to generate different binaries |
| 23 " from one VHDL source file. Unfortunately there is no preprocessor for VHDL | |
| 24 " available. If you don't like this, please remove the following lines. | |
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25 "syn match cDefine "^#ifdef[ ]\+[A-Za-z_]\+" |
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26 "syn match cDefine "^#endif" |
| 7 | 27 |
| 28 " case is not significant | |
| 29 syn case ignore | |
| 30 | |
| 31 " VHDL keywords | |
| 32 syn keyword vhdlStatement access after alias all assert | |
| 33 syn keyword vhdlStatement architecture array attribute | |
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34 syn keyword vhdlStatement assume assume_guarantee |
| 7 | 35 syn keyword vhdlStatement begin block body buffer bus |
| 36 syn keyword vhdlStatement case component configuration constant | |
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37 syn keyword vhdlStatement context cover |
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38 syn keyword vhdlStatement default disconnect downto |
| 7 | 39 syn keyword vhdlStatement elsif end entity exit |
| 40 syn keyword vhdlStatement file for function | |
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41 syn keyword vhdlStatement fairness force |
| 7 | 42 syn keyword vhdlStatement generate generic group guarded |
| 43 syn keyword vhdlStatement impure in inertial inout is | |
| 44 syn keyword vhdlStatement label library linkage literal loop | |
| 45 syn keyword vhdlStatement map | |
| 46 syn keyword vhdlStatement new next null | |
| 47 syn keyword vhdlStatement of on open others out | |
| 48 syn keyword vhdlStatement package port postponed procedure process pure | |
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49 syn keyword vhdlStatement parameter property protected |
| 7 | 50 syn keyword vhdlStatement range record register reject report return |
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51 syn keyword vhdlStatement release restrict restrict_guarantee |
| 7 | 52 syn keyword vhdlStatement select severity signal shared |
| 53 syn keyword vhdlStatement subtype | |
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54 syn keyword vhdlStatement sequence strong |
| 7 | 55 syn keyword vhdlStatement then to transport type |
| 56 syn keyword vhdlStatement unaffected units until use | |
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57 syn keyword vhdlStatement variable |
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58 syn keyword vhdlStatement vmode vprop vunit |
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Bram Moolenaar <bram@vim.org>
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59 syn keyword vhdlStatement wait when while with |
| 7 | 60 syn keyword vhdlStatement note warning error failure |
| 61 | |
| 62 " Special match for "if" and "else" since "else if" shouldn't be highlighted. | |
| 63 " The right keyword is "elsif" | |
| 64 syn match vhdlStatement "\<\(if\|else\)\>" | |
| 65 syn match vhdlNone "\<else\s\+if\>$" | |
| 66 syn match vhdlNone "\<else\s\+if\>\s" | |
| 67 | |
| 3557 | 68 " Predefined VHDL types |
| 7 | 69 syn keyword vhdlType bit bit_vector |
| 70 syn keyword vhdlType character boolean integer real time | |
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71 syn keyword vhdlType boolean_vector integer_vector real_vector time_vector |
| 7 | 72 syn keyword vhdlType string severity_level |
| 3557 | 73 " Predefined standard ieee VHDL types |
| 7 | 74 syn keyword vhdlType positive natural signed unsigned |
| 75 syn keyword vhdlType line text | |
| 76 syn keyword vhdlType std_logic std_logic_vector | |
| 77 syn keyword vhdlType std_ulogic std_ulogic_vector | |
| 78 " Predefined non standard VHDL types for Mentor Graphics Sys1076/QuickHDL | |
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79 "syn keyword vhdlType qsim_state qsim_state_vector |
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80 "syn keyword vhdlType qsim_12state qsim_12state_vector |
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81 "syn keyword vhdlType qsim_strength |
| 7 | 82 " Predefined non standard VHDL types for Alliance VLSI CAD |
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83 "syn keyword vhdlType mux_bit mux_vector reg_bit reg_vector wor_bit wor_vector |
| 7 | 84 |
| 85 " array attributes | |
| 86 syn match vhdlAttribute "\'high" | |
| 87 syn match vhdlAttribute "\'left" | |
| 88 syn match vhdlAttribute "\'length" | |
| 89 syn match vhdlAttribute "\'low" | |
| 90 syn match vhdlAttribute "\'range" | |
| 91 syn match vhdlAttribute "\'reverse_range" | |
| 92 syn match vhdlAttribute "\'right" | |
| 93 syn match vhdlAttribute "\'ascending" | |
| 94 " block attributes | |
| 95 syn match vhdlAttribute "\'behaviour" | |
| 96 syn match vhdlAttribute "\'structure" | |
| 97 syn match vhdlAttribute "\'simple_name" | |
| 98 syn match vhdlAttribute "\'instance_name" | |
| 99 syn match vhdlAttribute "\'path_name" | |
| 100 syn match vhdlAttribute "\'foreign" | |
| 101 " signal attribute | |
| 102 syn match vhdlAttribute "\'active" | |
| 103 syn match vhdlAttribute "\'delayed" | |
| 104 syn match vhdlAttribute "\'event" | |
| 105 syn match vhdlAttribute "\'last_active" | |
| 106 syn match vhdlAttribute "\'last_event" | |
| 107 syn match vhdlAttribute "\'last_value" | |
| 108 syn match vhdlAttribute "\'quiet" | |
| 109 syn match vhdlAttribute "\'stable" | |
| 110 syn match vhdlAttribute "\'transaction" | |
| 111 syn match vhdlAttribute "\'driving" | |
| 112 syn match vhdlAttribute "\'driving_value" | |
| 113 " type attributes | |
| 114 syn match vhdlAttribute "\'base" | |
| 115 syn match vhdlAttribute "\'high" | |
| 116 syn match vhdlAttribute "\'left" | |
| 117 syn match vhdlAttribute "\'leftof" | |
| 118 syn match vhdlAttribute "\'low" | |
| 119 syn match vhdlAttribute "\'pos" | |
| 120 syn match vhdlAttribute "\'pred" | |
| 121 syn match vhdlAttribute "\'rightof" | |
| 122 syn match vhdlAttribute "\'succ" | |
| 123 syn match vhdlAttribute "\'val" | |
| 124 syn match vhdlAttribute "\'image" | |
| 125 syn match vhdlAttribute "\'value" | |
| 126 | |
| 127 syn keyword vhdlBoolean true false | |
| 128 | |
| 129 " for this vector values case is significant | |
| 130 syn case match | |
| 131 " Values for standard VHDL types | |
| 132 syn match vhdlVector "\'[0L1HXWZU\-\?]\'" | |
| 133 " Values for non standard VHDL types qsim_12state for Mentor Graphics Sys1076/QuickHDL | |
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134 "syn keyword vhdlVector S0S S1S SXS S0R S1R SXR S0Z S1Z SXZ S0I S1I SXI |
| 7 | 135 syn case ignore |
| 136 | |
| 137 syn match vhdlVector "B\"[01_]\+\"" | |
| 138 syn match vhdlVector "O\"[0-7_]\+\"" | |
| 139 syn match vhdlVector "X\"[0-9a-f_]\+\"" | |
| 140 syn match vhdlCharacter "'.'" | |
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141 syn region vhdlString start=+"+ end=+"+ |
| 7 | 142 |
| 143 " floating numbers | |
| 144 syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>" | |
| 145 syn match vhdlNumber "-\=\<\d\+\.\d\+\>" | |
| 146 syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\=" | |
| 147 syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" | |
| 148 " integer numbers | |
| 149 syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>" | |
| 150 syn match vhdlNumber "-\=\<\d\+\>" | |
| 151 syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\=" | |
| 152 syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" | |
| 153 " operators | |
| 154 syn keyword vhdlOperator and nand or nor xor xnor | |
| 155 syn keyword vhdlOperator rol ror sla sll sra srl | |
| 156 syn keyword vhdlOperator mod rem abs not | |
| 157 syn match vhdlOperator "[&><=:+\-*\/|]" | |
| 158 syn match vhdlSpecial "[().,;]" | |
| 159 " time | |
| 160 syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" | |
| 161 syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" | |
| 162 | |
| 6823 | 163 syn keyword vhdlTodo contained TODO NOTE |
| 164 syn keyword vhdlFixme contained FIXME | |
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165 |
| 6823 | 166 " Regex for space is '\s' |
| 167 " Any number of spaces: \s* | |
| 168 " At least one space: \s+ | |
| 169 syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell | |
| 170 syn match vhdlComment "--.*" contains=vhdlTodo,vhdlFixme,@Spell | |
| 171 syn match vhdlPreProc "/\* synthesis .* \*/" | |
| 172 syn match vhdlPreProc "/\* pragma .* \*/" | |
| 173 syn match vhdlPreProc "/\* synopsys .* \*/" | |
| 174 syn match vhdlPreProc "--\s*synthesis .*" | |
| 175 syn match vhdlPreProc "--\s*pragma .*" | |
| 176 syn match vhdlPreProc "--\s*synopsys .*" | |
| 7 | 177 " syn match vhdlGlobal "[\'$#~!%@?\^\[\]{}\\]" |
| 178 | |
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179 "Modify the following as needed. The trade-off is performance versus functionality. |
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180 syn sync minlines=200 |
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181 |
| 7 | 182 " Define the default highlighting. |
| 183 " For version 5.7 and earlier: only when not done already | |
| 184 " For version 5.8 and later: only when an item doesn't have highlighting yet | |
| 185 if version >= 508 || !exists("did_vhdl_syntax_inits") | |
| 186 if version < 508 | |
| 187 let did_vhdl_syntax_inits = 1 | |
| 188 command -nargs=+ HiLink hi link <args> | |
| 189 else | |
| 190 command -nargs=+ HiLink hi def link <args> | |
| 191 endif | |
| 192 | |
| 6823 | 193 HiLink vhdlSpecial Special |
| 194 HiLink vhdlStatement Statement | |
| 195 HiLink vhdlCharacter Character | |
| 196 HiLink vhdlString String | |
| 197 HiLink vhdlVector Number | |
| 198 HiLink vhdlBoolean Number | |
| 199 HiLink vhdlTodo Todo | |
| 200 HiLink vhdlFixme Fixme | |
| 201 HiLink vhdlComment Comment | |
| 202 HiLink vhdlNumber Number | |
| 203 HiLink vhdlTime Number | |
| 204 HiLink vhdlType Type | |
| 205 HiLink vhdlOperator Operator | |
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Bram Moolenaar <bram@vim.org>
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206 " HiLink vhdlGlobal Error |
| 6823 | 207 HiLink vhdlAttribute Special |
| 208 HiLink vhdlPreProc PreProc | |
| 7 | 209 |
| 210 delcommand HiLink | |
| 211 endif | |
| 212 | |
| 213 let b:current_syntax = "vhdl" | |
| 214 | |
| 3312 | 215 let &cpo = s:cpo_save |
| 216 unlet s:cpo_save | |
| 7 | 217 " vim: ts=8 |