view runtime/ftplugin/systemverilog.vim @ 29163:9288c636ffa5 v8.2.5101

patch 8.2.5101: MS-Windows with MinGW: $CC may be "cc" instead of "gcc" Commit: https://github.com/vim/vim/commit/cf65d88ff844f042337dfd043e6e98f3b9270577 Author: Yegappan Lakshmanan <yegappan@yahoo.com> Date: Wed Jun 15 18:31:45 2022 +0100 patch 8.2.5101: MS-Windows with MinGW: $CC may be "cc" instead of "gcc" Problem: MS-Windows with MinGW: $CC may be "cc" instead of "gcc". Solution: Set $CC if it is not matching "clang". (Yegappan Lakshmanan, closes #10578)
author Bram Moolenaar <Bram@vim.org>
date Wed, 15 Jun 2022 19:45:04 +0200
parents 11b656e74444
children
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" Vim filetype plugin file
" Language:    SystemVerilog
" Maintainer:  kocha <kocha.lsifrontend@gmail.com>
" Last Change: 07-May-2021

if exists("b:did_ftplugin")
  finish
endif

" Behaves just like Verilog
runtime! ftplugin/verilog.vim

let s:cpo_save = &cpo
set cpo&vim

" Add SystemVerilog keywords for matchit plugin.
if exists("loaded_matchit")
  let b:match_words =
    \ '\<begin\>:\<end\>,' .
    \ '\<case\>\|\<casex\>\|\<casez\>:\<endcase\>,' .
    \ '\<module\>:\<endmodule\>,' .
    \ '\<if\>:`\@<!\<else\>,' .
    \ '\<function\>:\<endfunction\>,' .
    \ '`ifn\?def\>:`elsif\>:`else\>:`endif\>,' .
    \ '\<task\>:\<endtask\>,' .
    \ '\<specify\>:\<endspecify\>,' .
    \ '\<config\>:\<endconfig\>,' .
    \ '\<generate\>:\<endgenerate\>,' .
    \ '\<fork\>:\<join\>\|\<join_any\>\|\<join_none\>,' .
    \ '\<primitive\>:\<endprimitive\>,' .
    \ '\<table\>:\<endtable\>,' .
    \ '\<checker\>:\<endchecker\>,' .
    \ '\<class\>:\<endclass\>,' .
    \ '\<clocking\>:\<endclocking\>,' .
    \ '\<group\>:\<endgroup\>,' .
    \ '\<interface\>:\<endinterface\>,' .
    \ '\<package\>:\<endpackage\>,' .
    \ '\<program\>:\<endprogram\>,' .
    \ '\<property\>:\<endproperty\>,' .
    \ '\<sequence\>:\<endsequence\>'
endif

let &cpo = s:cpo_save
unlet s:cpo_save