view runtime/ftplugin/systemverilog.vim @ 24665:661d15592d3c v8.2.2871

patch 8.2.2871: unnessary VIM_ISDIGIT() calls, badly indented code Commit: https://github.com/vim/vim/commit/4781d6fd8670af415c3b78f00d70036af85bd286 Author: Dominique Pelle <dominique.pelle@gmail.com> Date: Tue May 18 21:46:31 2021 +0200 patch 8.2.2871: unnessary VIM_ISDIGIT() calls, badly indented code Problem: Unnessary VIM_ISDIGIT() calls, badly indented code. Solution: Call skipdigits() on the next character. Improve indenting. (Dominique Pell?, closes #8227)
author Bram Moolenaar <Bram@vim.org>
date Tue, 18 May 2021 22:00:05 +0200
parents 840665e74421
children 11b656e74444
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" Vim filetype plugin file
" Language:    SystemVerilog
" Maintainer:  kocha <kocha.lsifrontend@gmail.com>
" Last Change: 07-May-2021

if exists("b:did_ftplugin")
  finish
endif

" Behaves just like Verilog
runtime! ftplugin/verilog.vim

let s:cpo_save = &cpo
set cpo&vim

" Add SystemVerilog keywords for matchit plugin.
if exists("loaded_matchit")
  let b:match_words =
    \ '\<begin\>:\<end\>,' .
    \ '\<case\>\|\<casex\>\|\<casez\>:\<endcase\>,' .
    \ '\<module\>:\<endmodule\>,' .
    \ '\<if\>:`\@<!\<else\>,' .
    \ '\<function\>:\<endfunction\>,' .
    \ '`ifn\?def\>:`elsif\>:`else\>:`endif\>,' .
    \ '\<task\>:\<endtask\>,' .
    \ '\<specify\>:\<endspecify\>,' .
    \ '\<config\>:\<endconfig\>,' .
    \ '\<generate\>:\<endgenerate\>,' .
    \ '\<fork\>:\<join\>\|\<join_any\>\|\<join_none\>,' .
    \ '\<primitive\>:\<endprimitive\>,' .
    \ '\<table\>:\<endtable\>,' .
    \ '\<checker\>:\<endchecker\>,' .
    \ '\<class\>:\<endclass\>,' .
    \ '\<clocking\>:\<endclocking\>,' .
    \ '\<gruop\>:\<endgruop\>,' .
    \ '\<interface\>:\<endinterface\>,' .
    \ '\<package\>:\<endpackage\>,' .
    \ '\<program\>:\<endprogram\>,' .
    \ '\<property\>:\<endproperty\>,' .
    \ '\<sequence\>:\<endsequence\>'
endif

let &cpo = s:cpo_save
unlet s:cpo_save