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Update runtime files Commit: https://github.com/vim/vim/commit/ff78155aa1755aced96a3b343e81939c94aac721 Author: Bram Moolenaar <Bram@vim.org> Date: Thu Mar 19 20:37:11 2020 +0100 Update runtime files
author Bram Moolenaar <Bram@vim.org>
date Thu, 19 Mar 2020 20:45:06 +0100
parents e751b5c9dff3
children 1908e92b02fd
comparison
equal deleted inserted replaced
19720:69b650ef768a 19721:bceeded72898
1 " Vim syntax file 1 " Vim syntax file
2 " Language: VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language] 2 " Language: VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language]
3 " Maintainer: Daniel Kho <daniel.kho@tauhop.com> 3 " Maintainer: Daniel Kho <daniel.kho@logik.haus>
4 " Previous Maintainer: Czo <Olivier.Sirol@lip6.fr> 4 " Previous Maintainer: Czo <Olivier.Sirol@lip6.fr>
5 " Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn> 5 " Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
6 " Last Changed: 2018 May 06 by Daniel Kho 6 " Last Changed: 2020 Mar 09 by Daniel Kho
7 7
8 " quit when a syntax file was already loaded 8 " quit when a syntax file was already loaded
9 if exists("b:current_syntax") 9 if exists("b:current_syntax")
10 finish 10 finish
11 endif 11 endif
41 syn keyword vhdlStatement subtype 41 syn keyword vhdlStatement subtype
42 syn keyword vhdlStatement sequence strong 42 syn keyword vhdlStatement sequence strong
43 syn keyword vhdlStatement then to transport type 43 syn keyword vhdlStatement then to transport type
44 syn keyword vhdlStatement unaffected units until use 44 syn keyword vhdlStatement unaffected units until use
45 syn keyword vhdlStatement variable 45 syn keyword vhdlStatement variable
46 " VHDL-2017 interface 46 " VHDL-2019 interface
47 syn keyword vhdlStatement view 47 syn keyword vhdlStatement view
48 syn keyword vhdlStatement vmode vprop vunit 48 syn keyword vhdlStatement vmode vprop vunit
49 syn keyword vhdlStatement wait when while with 49 syn keyword vhdlStatement wait when while with
50 syn keyword vhdlStatement note warning error failure 50 syn keyword vhdlStatement note warning error failure
51 51
122 syn match vhdlAttribute "\'rightof" 122 syn match vhdlAttribute "\'rightof"
123 syn match vhdlAttribute "\'succ" 123 syn match vhdlAttribute "\'succ"
124 syn match vhdlAttribute "\'val" 124 syn match vhdlAttribute "\'val"
125 syn match vhdlAttribute "\'image" 125 syn match vhdlAttribute "\'image"
126 syn match vhdlAttribute "\'value" 126 syn match vhdlAttribute "\'value"
127 " VHDL-2017 interface attribute 127 " VHDL-2019 interface attribute
128 syn match vhdlAttribute "\'converse" 128 syn match vhdlAttribute "\'converse"
129 129
130 syn keyword vhdlBoolean true false 130 syn keyword vhdlBoolean true false
131 131
132 " for this vector values case is significant 132 " for this vector values case is significant
165 165
166 " Assignment operators 166 " Assignment operators
167 syn match vhdlOperator "<=\|:=" 167 syn match vhdlOperator "<=\|:="
168 syn match vhdlOperator "=>" 168 syn match vhdlOperator "=>"
169 169
170 " VHDL-2017 concurrent signal association (spaceship) operator 170 " VHDL-202x concurrent signal association (spaceship) operator
171 syn match vhdlOperator "<=>" 171 syn match vhdlOperator "<=>"
172 172
173 " VHDL-2008 conversion, matching equality/non-equality operators 173 " VHDL-2008 conversion, matching equality/non-equality operators
174 syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>=" 174 syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>="
175 175
186 syn match vhdlError "[&+\-\/\\]\+\(>\)" 186 syn match vhdlError "[&+\-\/\\]\+\(>\)"
187 syn match vhdlError "\(<\)[&+\-\/\\]\+" 187 syn match vhdlError "\(<\)[&+\-\/\\]\+"
188 syn match vhdlError "[>=&+\-\/\\]\+\(<\)" 188 syn match vhdlError "[>=&+\-\/\\]\+\(<\)"
189 " Covers most operators 189 " Covers most operators
190 " support negative sign after operators. E.g. q<=-b; 190 " support negative sign after operators. E.g. q<=-b;
191 " Supports VHDL-2017 spaceship (concurrent simple signal association). 191 " Supports VHDL-202x spaceship (concurrent simple signal association).
192 syn match vhdlError "\(<=\)[<=&+\*\\?:]\+" 192 syn match vhdlError "\(<=\)[<=&+\*\\?:]\+"
193 syn match vhdlError "[>=&+\-\*\\:]\+\(=>\)" 193 syn match vhdlError "[>=&+\-\*\\:]\+\(=>\)"
194 syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|:=\|=>\)[<>=&+\*\\?:]\+" 194 syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|:=\|=>\)[<>=&+\*\\?:]\+"
195 syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\)" 195 syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\)"
196 syn match vhdlError "\(?<\|?>\)[<>&+\*\/\\?:]\+" 196 syn match vhdlError "\(?<\|?>\)[<>&+\*\/\\?:]\+"