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comparison runtime/syntax/vhdl.vim @ 5362:ab1508486b12

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Update runtime files. Add support for J.
author Bram Moolenaar <bram@vim.org>
date Sun, 22 Sep 2013 14:42:24 +0200
parents 9cb3a75a20b9
children 0303182665d5
comparison
equal deleted inserted replaced
5361:f0a6eb929df1 5362:ab1508486b12
1 " Vim syntax file 1 " Vim syntax file
2 " Language: VHDL 2 " Language: VHDL
3 " Maintainer: Czo <Olivier.Sirol@lip6.fr> 3 " Maintainer: Daniel Kho <daniel.kho@tauhop.com>
4 " Previous Maintainer: Czo <Olivier.Sirol@lip6.fr>
4 " Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn> 5 " Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
5 " Last Change: 2012 Jun 01 6 " Last Changed: 2012 Feb 03 by Thilo Six
6 " (Dominique Pelle added @Spell) 7 " $Id: vhdl.vim,v 1.1 2004/06/13 15:34:56 vimboss Exp $
7 8
8 " VHSIC Hardware Description Language 9 " VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
9 " Very High Scale Integrated Circuit
10 10
11 " For version 5.x: Clear all syntax items 11 " For version 5.x: Clear all syntax items
12 " For version 6.x: Quit when a syntax file was already loaded 12 " For version 6.x: Quit when a syntax file was already loaded
13 if version < 600 13 if version < 600
14 syntax clear 14 syntax clear
20 set cpo&vim 20 set cpo&vim
21 21
22 " This is not VHDL. I use the C-Preprocessor cpp to generate different binaries 22 " This is not VHDL. I use the C-Preprocessor cpp to generate different binaries
23 " from one VHDL source file. Unfortunately there is no preprocessor for VHDL 23 " from one VHDL source file. Unfortunately there is no preprocessor for VHDL
24 " available. If you don't like this, please remove the following lines. 24 " available. If you don't like this, please remove the following lines.
25 syn match cDefine "^#ifdef[ ]\+[A-Za-z_]\+" 25 "syn match cDefine "^#ifdef[ ]\+[A-Za-z_]\+"
26 syn match cDefine "^#endif" 26 "syn match cDefine "^#endif"
27 27
28 " case is not significant 28 " case is not significant
29 syn case ignore 29 syn case ignore
30 30
31 " VHDL keywords 31 " VHDL keywords
32 syn keyword vhdlStatement access after alias all assert 32 syn keyword vhdlStatement access after alias all assert
33 syn keyword vhdlStatement architecture array attribute 33 syn keyword vhdlStatement architecture array attribute
34 syn keyword vhdlStatement assume assume_guarantee
34 syn keyword vhdlStatement begin block body buffer bus 35 syn keyword vhdlStatement begin block body buffer bus
35 syn keyword vhdlStatement case component configuration constant 36 syn keyword vhdlStatement case component configuration constant
36 syn keyword vhdlStatement disconnect downto 37 syn keyword vhdlStatement context cover
38 syn keyword vhdlStatement default disconnect downto
37 syn keyword vhdlStatement elsif end entity exit 39 syn keyword vhdlStatement elsif end entity exit
38 syn keyword vhdlStatement file for function 40 syn keyword vhdlStatement file for function
41 syn keyword vhdlStatement fairness force
39 syn keyword vhdlStatement generate generic group guarded 42 syn keyword vhdlStatement generate generic group guarded
40 syn keyword vhdlStatement impure in inertial inout is 43 syn keyword vhdlStatement impure in inertial inout is
41 syn keyword vhdlStatement label library linkage literal loop 44 syn keyword vhdlStatement label library linkage literal loop
42 syn keyword vhdlStatement map 45 syn keyword vhdlStatement map
43 syn keyword vhdlStatement new next null 46 syn keyword vhdlStatement new next null
44 syn keyword vhdlStatement of on open others out 47 syn keyword vhdlStatement of on open others out
45 syn keyword vhdlStatement package port postponed procedure process pure 48 syn keyword vhdlStatement package port postponed procedure process pure
49 syn keyword vhdlStatement parameter property protected
46 syn keyword vhdlStatement range record register reject report return 50 syn keyword vhdlStatement range record register reject report return
51 syn keyword vhdlStatement release restrict restrict_guarantee
47 syn keyword vhdlStatement select severity signal shared 52 syn keyword vhdlStatement select severity signal shared
48 syn keyword vhdlStatement subtype 53 syn keyword vhdlStatement subtype
54 syn keyword vhdlStatement sequence strong
49 syn keyword vhdlStatement then to transport type 55 syn keyword vhdlStatement then to transport type
50 syn keyword vhdlStatement unaffected units until use 56 syn keyword vhdlStatement unaffected units until use
51 syn keyword vhdlStatement variable wait when while with 57 syn keyword vhdlStatement variable
58 syn keyword vhdlStatement vmode vprop vunit
59 syn keyword vhdlStatement wait when while with
52 syn keyword vhdlStatement note warning error failure 60 syn keyword vhdlStatement note warning error failure
53 61
54 " Special match for "if" and "else" since "else if" shouldn't be highlighted. 62 " Special match for "if" and "else" since "else if" shouldn't be highlighted.
55 " The right keyword is "elsif" 63 " The right keyword is "elsif"
56 syn match vhdlStatement "\<\(if\|else\)\>" 64 syn match vhdlStatement "\<\(if\|else\)\>"
58 syn match vhdlNone "\<else\s\+if\>\s" 66 syn match vhdlNone "\<else\s\+if\>\s"
59 67
60 " Predefined VHDL types 68 " Predefined VHDL types
61 syn keyword vhdlType bit bit_vector 69 syn keyword vhdlType bit bit_vector
62 syn keyword vhdlType character boolean integer real time 70 syn keyword vhdlType character boolean integer real time
71 syn keyword vhdlType boolean_vector integer_vector real_vector time_vector
63 syn keyword vhdlType string severity_level 72 syn keyword vhdlType string severity_level
64 " Predefined standard ieee VHDL types 73 " Predefined standard ieee VHDL types
65 syn keyword vhdlType positive natural signed unsigned 74 syn keyword vhdlType positive natural signed unsigned
66 syn keyword vhdlType line text 75 syn keyword vhdlType line text
67 syn keyword vhdlType std_logic std_logic_vector 76 syn keyword vhdlType std_logic std_logic_vector
68 syn keyword vhdlType std_ulogic std_ulogic_vector 77 syn keyword vhdlType std_ulogic std_ulogic_vector
69 " Predefined non standard VHDL types for Mentor Graphics Sys1076/QuickHDL 78 " Predefined non standard VHDL types for Mentor Graphics Sys1076/QuickHDL
70 syn keyword vhdlType qsim_state qsim_state_vector 79 "syn keyword vhdlType qsim_state qsim_state_vector
71 syn keyword vhdlType qsim_12state qsim_12state_vector 80 "syn keyword vhdlType qsim_12state qsim_12state_vector
72 syn keyword vhdlType qsim_strength 81 "syn keyword vhdlType qsim_strength
73 " Predefined non standard VHDL types for Alliance VLSI CAD 82 " Predefined non standard VHDL types for Alliance VLSI CAD
74 syn keyword vhdlType mux_bit mux_vector reg_bit reg_vector wor_bit wor_vector 83 "syn keyword vhdlType mux_bit mux_vector reg_bit reg_vector wor_bit wor_vector
75 84
76 " array attributes 85 " array attributes
77 syn match vhdlAttribute "\'high" 86 syn match vhdlAttribute "\'high"
78 syn match vhdlAttribute "\'left" 87 syn match vhdlAttribute "\'left"
79 syn match vhdlAttribute "\'length" 88 syn match vhdlAttribute "\'length"
120 " for this vector values case is significant 129 " for this vector values case is significant
121 syn case match 130 syn case match
122 " Values for standard VHDL types 131 " Values for standard VHDL types
123 syn match vhdlVector "\'[0L1HXWZU\-\?]\'" 132 syn match vhdlVector "\'[0L1HXWZU\-\?]\'"
124 " Values for non standard VHDL types qsim_12state for Mentor Graphics Sys1076/QuickHDL 133 " Values for non standard VHDL types qsim_12state for Mentor Graphics Sys1076/QuickHDL
125 syn keyword vhdlVector S0S S1S SXS S0R S1R SXR S0Z S1Z SXZ S0I S1I SXI 134 "syn keyword vhdlVector S0S S1S SXS S0R S1R SXR S0Z S1Z SXZ S0I S1I SXI
126 syn case ignore 135 syn case ignore
127 136
128 syn match vhdlVector "B\"[01_]\+\"" 137 syn match vhdlVector "B\"[01_]\+\""
129 syn match vhdlVector "O\"[0-7_]\+\"" 138 syn match vhdlVector "O\"[0-7_]\+\""
130 syn match vhdlVector "X\"[0-9a-f_]\+\"" 139 syn match vhdlVector "X\"[0-9a-f_]\+\""
131 syn match vhdlCharacter "'.'" 140 syn match vhdlCharacter "'.'"
132 syn region vhdlString start=+"+ end=+"+ contains=@Spell 141 syn region vhdlString start=+"+ end=+"+
133 142
134 " floating numbers 143 " floating numbers
135 syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>" 144 syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>"
136 syn match vhdlNumber "-\=\<\d\+\.\d\+\>" 145 syn match vhdlNumber "-\=\<\d\+\.\d\+\>"
137 syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\=" 146 syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\="
149 syn match vhdlSpecial "[().,;]" 158 syn match vhdlSpecial "[().,;]"
150 " time 159 " time
151 syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 160 syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
152 syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 161 syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
153 162
154 syn match vhdlComment "--.*$" contains=@Spell 163 syn keyword vhdlTodo contained TODO FIXME
164
165 syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,@Spell
166 syn match vhdlComment "--.*" contains=vhdlTodo,@Spell
155 " syn match vhdlGlobal "[\'$#~!%@?\^\[\]{}\\]" 167 " syn match vhdlGlobal "[\'$#~!%@?\^\[\]{}\\]"
168
169 "Modify the following as needed. The trade-off is performance versus functionality.
170 syn sync minlines=200
156 171
157 " Define the default highlighting. 172 " Define the default highlighting.
158 " For version 5.7 and earlier: only when not done already 173 " For version 5.7 and earlier: only when not done already
159 " For version 5.8 and later: only when an item doesn't have highlighting yet 174 " For version 5.8 and later: only when an item doesn't have highlighting yet
160 if version >= 508 || !exists("did_vhdl_syntax_inits") 175 if version >= 508 || !exists("did_vhdl_syntax_inits")
163 command -nargs=+ HiLink hi link <args> 178 command -nargs=+ HiLink hi link <args>
164 else 179 else
165 command -nargs=+ HiLink hi def link <args> 180 command -nargs=+ HiLink hi def link <args>
166 endif 181 endif
167 182
168 HiLink cDefine PreProc 183 " HiLink cDefine PreProc
169 HiLink vhdlSpecial Special 184 HiLink vhdlSpecial Special
170 HiLink vhdlStatement Statement 185 HiLink vhdlStatement Statement
171 HiLink vhdlCharacter String 186 HiLink vhdlCharacter Character
172 HiLink vhdlString String 187 HiLink vhdlString String
173 HiLink vhdlVector String 188 HiLink vhdlVector Number
174 HiLink vhdlBoolean String 189 HiLink vhdlBoolean Number
190 HiLink vhdlTodo Todo
175 HiLink vhdlComment Comment 191 HiLink vhdlComment Comment
176 HiLink vhdlNumber String 192 HiLink vhdlNumber Number
177 HiLink vhdlTime String 193 HiLink vhdlTime Number
178 HiLink vhdlType Type 194 HiLink vhdlType Type
179 HiLink vhdlOperator Type 195 HiLink vhdlOperator Special
180 HiLink vhdlGlobal Error 196 " HiLink vhdlGlobal Error
181 HiLink vhdlAttribute Type 197 HiLink vhdlAttribute Type
182 198
183 delcommand HiLink 199 delcommand HiLink
184 endif 200 endif
185 201