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comparison runtime/syntax/verilogams.vim @ 1621:82b5078be2dd

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updated for version 7.2a
author vimboss
date Tue, 24 Jun 2008 21:56:24 +0000
parents 66080ac5dab7
children 43efa4f5a8ea
comparison
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1620:73fe8baea242 1621:82b5078be2dd
1 " Vim syntax file 1 " Vim syntax file
2 " Language: Verilog-AMS 2 " Language: Verilog-AMS
3 " Maintainer: S. Myles Prather <smprather@gmail.com> 3 " Maintainer: S. Myles Prather <smprather@gmail.com>
4 " Last Update: Sun Aug 14 03:58:00 CST 2003 4 "
5 " Version 1.1 S. Myles Prather <smprather@gmail.com>
6 " Moved some keywords to the type category.
7 " Added the metrix suffixes to the number matcher.
8 " Version 1.2 Prasanna Tamhankar <pratam@gmail.com>
9 " Minor reserved keyword updates.
10 " Last Update: Thursday September 15 15:36:03 CST 2005
5 11
6 " For version 5.x: Clear all syntax items 12 " For version 5.x: Clear all syntax items
7 " For version 6.x: Quit when a syntax file was already loaded 13 " For version 6.x: Quit when a syntax file was already loaded
8 if version < 600 14 if version < 600
9 syntax clear 15 syntax clear
19 endif 25 endif
20 26
21 " Annex B.1 'All keywords' 27 " Annex B.1 'All keywords'
22 syn keyword verilogamsStatement above abs absdelay acos acosh ac_stim 28 syn keyword verilogamsStatement above abs absdelay acos acosh ac_stim
23 syn keyword verilogamsStatement always analog analysis and asin 29 syn keyword verilogamsStatement always analog analysis and asin
24 syn keyword verilogamsStatement asinh assign atan atan2 atanh branch 30 syn keyword verilogamsStatement asinh assign atan atan2 atanh
25 syn keyword verilogamsStatement buf bufif1 ceil cmos 31 syn keyword verilogamsStatement buf bufif0 bufif1 ceil cmos connectmodule
26 syn keyword verilogamsStatement connectrules cos cosh cross ddt ddx deassign 32 syn keyword verilogamsStatement connectrules cos cosh cross ddt ddx deassign
27 syn keyword verilogamsStatement defparam disable discipline 33 syn keyword verilogamsStatement defparam disable discipline
28 syn keyword verilogamsStatement driver_update edge enddiscipline 34 syn keyword verilogamsStatement driver_update edge enddiscipline
29 syn keyword verilogamsStatement endconnectrules endmodule endfunction 35 syn keyword verilogamsStatement endconnectrules endmodule endfunction endgenerate
30 syn keyword verilogamsStatement endnature endparamset endprimitive endspecify 36 syn keyword verilogamsStatement endnature endparamset endprimitive endspecify
31 syn keyword verilogamsStatement endtable endtask event exp final_step 37 syn keyword verilogamsStatement endtable endtask event exp final_step
32 syn keyword verilogamsStatement flicker_noise floor flow force fork 38 syn keyword verilogamsStatement flicker_noise floor flow force fork
33 syn keyword verilogamsStatement function generate genvar highz0 39 syn keyword verilogamsStatement function generate highz0
34 syn keyword verilogamsStatement highz1 hypot idt idtmod if ifnone initial 40 syn keyword verilogamsStatement highz1 hypot idt idtmod if ifnone inf initial
35 syn keyword verilogamsStatement initial_step inout input join 41 syn keyword verilogamsStatement initial_step inout input join
36 syn keyword verilogamsStatement laplace_nd laplace_np laplace_zd laplace_zp 42 syn keyword verilogamsStatement laplace_nd laplace_np laplace_zd laplace_zp
37 syn keyword verilogamsStatement large last_crossing limexp ln localparam log 43 syn keyword verilogamsStatement large last_crossing limexp ln localparam log
38 syn keyword verilogamsStatement macromodule max medium min module nand nature 44 syn keyword verilogamsStatement macromodule max medium min module nand nature
39 syn keyword verilogamsStatement negedge net_resolution nmos noise_table nor not 45 syn keyword verilogamsStatement negedge net_resolution nmos noise_table nor not
40 syn keyword verilogamsStatement notif0 notif1 or output paramset pmos 46 syn keyword verilogamsStatement notif0 notif1 or output paramset pmos
41 syn keyword verilogamsType parameter real integer electrical input output 47 syn keyword verilogamsType parameter real integer electrical input output
42 syn keyword verilogamsType inout reg tri tri0 tri1 triand trior trireg 48 syn keyword verilogamsType inout reg tri tri0 tri1 triand trior trireg
43 syn keyword verilogamsType string from exclude aliasparam ground 49 syn keyword verilogamsType string from exclude aliasparam ground genvar
50 syn keyword verilogamsType branch time realtime
44 syn keyword verilogamsStatement posedge potential pow primitive pull0 pull1 51 syn keyword verilogamsStatement posedge potential pow primitive pull0 pull1
45 syn keyword verilogamsStatement pullup pulldown rcmos release 52 syn keyword verilogamsStatement pullup pulldown rcmos release
46 syn keyword verilogamsStatement rnmos rpmos rtran rtranif0 rtranif1 53 syn keyword verilogamsStatement rnmos rpmos rtran rtranif0 rtranif1
47 syn keyword verilogamsStatement scalared sin sinh slew small specify specparam 54 syn keyword verilogamsStatement scalared sin sinh slew small specify specparam
48 syn keyword verilogamsStatement sqrt strong0 strong1 supply0 supply1 55 syn keyword verilogamsStatement sqrt strong0 strong1 supply0 supply1
49 syn keyword verilogamsStatement table tan tanh task time timer tran tranif0 56 syn keyword verilogamsStatement table tan tanh task timer tran tranif0
50 syn keyword verilogamsStatement tranif1 transition 57 syn keyword verilogamsStatement tranif1 transition
51 syn keyword verilogamsStatement vectored wait wand weak0 weak1 58 syn keyword verilogamsStatement vectored wait wand weak0 weak1
52 syn keyword verilogamsStatement white_noise wire wor wreal xnor xor zi_nd 59 syn keyword verilogamsStatement white_noise wire wor wreal xnor xor zi_nd
53 syn keyword verilogamsStatement zi_np zi_zd 60 syn keyword verilogamsStatement zi_np zi_zd zi_zp
54 syn keyword verilogamsRepeat forever repeat while for 61 syn keyword verilogamsRepeat forever repeat while for
55 syn keyword verilogamsLabel begin end 62 syn keyword verilogamsLabel begin end
56 syn keyword verilogamsConditional if else case casex casez default endcase 63 syn keyword verilogamsConditional if else case casex casez default endcase
57 syn match verilogamsConstant ":inf"lc=1 64 syn match verilogamsConstant ":inf"lc=1
58 syn match verilogamsConstant "-inf"lc=1 65 syn match verilogamsConstant "-inf"lc=1
93 100
94 syn match verilogamsNumber "\(\<\d\+\|\)'[bB]\s*[0-1_xXzZ?]\+\>" 101 syn match verilogamsNumber "\(\<\d\+\|\)'[bB]\s*[0-1_xXzZ?]\+\>"
95 syn match verilogamsNumber "\(\<\d\+\|\)'[oO]\s*[0-7_xXzZ?]\+\>" 102 syn match verilogamsNumber "\(\<\d\+\|\)'[oO]\s*[0-7_xXzZ?]\+\>"
96 syn match verilogamsNumber "\(\<\d\+\|\)'[dD]\s*[0-9_xXzZ?]\+\>" 103 syn match verilogamsNumber "\(\<\d\+\|\)'[dD]\s*[0-9_xXzZ?]\+\>"
97 syn match verilogamsNumber "\(\<\d\+\|\)'[hH]\s*[0-9a-fA-F_xXzZ?]\+\>" 104 syn match verilogamsNumber "\(\<\d\+\|\)'[hH]\s*[0-9a-fA-F_xXzZ?]\+\>"
98 syn match verilogamsNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)\>" 105 syn match verilogamsNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)[TGMKkmunpfa]\=\>"
99 106
100 syn region verilogamsString start=+"+ skip=+\\"+ end=+"+ contains=verilogamsEscape 107 syn region verilogamsString start=+"+ skip=+\\"+ end=+"+ contains=verilogamsEscape
101 syn match verilogamsEscape +\\[nt"\\]+ contained 108 syn match verilogamsEscape +\\[nt"\\]+ contained
102 syn match verilogamsEscape "\\\o\o\=\o\=" contained 109 syn match verilogamsEscape "\\\o\o\=\o\=" contained
103 110