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annotate runtime/syntax/systemverilog.vim @ 33956:e0535b3b9d77

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runtime(racket): update Racket runtime files (#13693) Commit: https://github.com/vim/vim/commit/5eb9cb53d619f89251d22299e2cb4f21918d9d38 Author: D. Ben Knoble <ben.knoble+github@gmail.com> Date: Sat Dec 16 08:24:15 2023 -0500 runtime(racket): update Racket runtime files (https://github.com/vim/vim/issues/13693) This brings the included Racket runtime files to commit 43bfc87 (update headers, 2023-12-15) of https://github.com/benknoble/vim-racket. Note that not all files from that repository are included. (In particular, the ftdetect script is omitted for now.) Signed-off-by: D. Ben Knoble <ben.knoble+github@gmail.com> Signed-off-by: Christian Brabandt <cb@256bit.org>
author Christian Brabandt <cb@256bit.org>
date Sat, 16 Dec 2023 14:30:06 +0100
parents 46763b01cd9a
children
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1 " Vim syntax file
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2 " Language: SystemVerilog
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3 " Maintainer: kocha <kocha.lsifrontend@gmail.com>
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4 " Last Change: 12-Aug-2013.
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5
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6 " quit when a syntax file was already loaded
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7 if exists("b:current_syntax")
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8 finish
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9 endif
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10
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11 " Read in Verilog syntax files
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12 runtime! syntax/verilog.vim
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13 unlet b:current_syntax
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14
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15 " IEEE1800-2005
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16 syn keyword systemverilogStatement always_comb always_ff always_latch
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17 syn keyword systemverilogStatement class endclass new
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18 syn keyword systemverilogStatement virtual local const protected
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19 syn keyword systemverilogStatement package endpackage
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20 syn keyword systemverilogStatement rand randc constraint randomize
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21 syn keyword systemverilogStatement with inside dist
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22 syn keyword systemverilogStatement sequence endsequence randsequence
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23 syn keyword systemverilogStatement srandom
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24 syn keyword systemverilogStatement logic bit byte
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25 syn keyword systemverilogStatement int longint shortint
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26 syn keyword systemverilogStatement struct packed
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27 syn keyword systemverilogStatement final
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28 syn keyword systemverilogStatement import export
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29 syn keyword systemverilogStatement context pure
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30 syn keyword systemverilogStatement void shortreal chandle string
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31 syn keyword systemverilogStatement clocking endclocking iff
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32 syn keyword systemverilogStatement interface endinterface modport
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33 syn keyword systemverilogStatement cover covergroup coverpoint endgroup
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34 syn keyword systemverilogStatement property endproperty
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35 syn keyword systemverilogStatement program endprogram
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36 syn keyword systemverilogStatement bins binsof illegal_bins ignore_bins
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37 syn keyword systemverilogStatement alias matches solve static assert
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38 syn keyword systemverilogStatement assume super before expect bind
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39 syn keyword systemverilogStatement extends null tagged extern this
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40 syn keyword systemverilogStatement first_match throughout timeprecision
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41 syn keyword systemverilogStatement timeunit type union
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42 syn keyword systemverilogStatement uwire var cross ref wait_order intersect
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43 syn keyword systemverilogStatement wildcard within
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44
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45 syn keyword systemverilogTypeDef typedef enum
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46
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47 syn keyword systemverilogConditional randcase
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48 syn keyword systemverilogConditional unique priority
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49
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50 syn keyword systemverilogRepeat return break continue
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51 syn keyword systemverilogRepeat do foreach
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52
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53 syn keyword systemverilogLabel join_any join_none forkjoin
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54
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55 " IEEE1800-2009 add
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56 syn keyword systemverilogStatement checker endchecker
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57 syn keyword systemverilogStatement accept_on reject_on
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58 syn keyword systemverilogStatement sync_accept_on sync_reject_on
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59 syn keyword systemverilogStatement eventually nexttime until until_with
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60 syn keyword systemverilogStatement s_always s_eventually s_nexttime s_until s_until_with
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61 syn keyword systemverilogStatement let untyped
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62 syn keyword systemverilogStatement strong weak
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63 syn keyword systemverilogStatement restrict global implies
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64
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65 syn keyword systemverilogConditional unique0
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66
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67 " IEEE1800-2012 add
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68 syn keyword systemverilogStatement implements
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69 syn keyword systemverilogStatement interconnect soft nettype
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70
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71 " Define the default highlighting.
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72
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73 " The default highlighting.
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74 hi def link systemverilogStatement Statement
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75 hi def link systemverilogTypeDef TypeDef
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76 hi def link systemverilogConditional Conditional
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77 hi def link systemverilogRepeat Repeat
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78 hi def link systemverilogLabel Label
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79 hi def link systemverilogGlobal Define
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80 hi def link systemverilogNumber Number
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81
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82
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83 let b:current_syntax = "systemverilog"
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84
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85 " vim: ts=8