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7
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1 " Vim syntax file
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2 " Language: Verilog
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1120
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3 " Maintainer: Mun Johl <Mun.Johl@emulex.com>
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4 " Last Update: Fri Oct 13 11:44:32 PDT 2006
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7
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5
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6 " For version 5.x: Clear all syntax items
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7 " For version 6.x: Quit when a syntax file was already loaded
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8 if version < 600
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9 syntax clear
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10 elseif exists("b:current_syntax")
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11 finish
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12 endif
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13
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14 " Set the local value of the 'iskeyword' option
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15 if version >= 600
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16 setlocal iskeyword=@,48-57,_,192-255
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17 else
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18 set iskeyword=@,48-57,_,192-255
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19 endif
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20
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21 " A bunch of useful Verilog keywords
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22
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23 syn keyword verilogStatement always and assign automatic buf
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24 syn keyword verilogStatement bufif0 bufif1 cell cmos
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25 syn keyword verilogStatement config deassign defparam design
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26 syn keyword verilogStatement disable edge endconfig
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27 syn keyword verilogStatement endfunction endgenerate endmodule
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28 syn keyword verilogStatement endprimitive endspecify endtable endtask
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29 syn keyword verilogStatement event force function
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30 syn keyword verilogStatement generate genvar highz0 highz1 ifnone
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31 syn keyword verilogStatement incdir include initial inout input
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32 syn keyword verilogStatement instance integer large liblist
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33 syn keyword verilogStatement library localparam macromodule medium
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34 syn keyword verilogStatement module nand negedge nmos nor
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35 syn keyword verilogStatement noshowcancelled not notif0 notif1 or
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36 syn keyword verilogStatement output parameter pmos posedge primitive
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37 syn keyword verilogStatement pull0 pull1 pulldown pullup
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38 syn keyword verilogStatement pulsestyle_onevent pulsestyle_ondetect
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39 syn keyword verilogStatement rcmos real realtime reg release
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40 syn keyword verilogStatement rnmos rpmos rtran rtranif0 rtranif1
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41 syn keyword verilogStatement scalared showcancelled signed small
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42 syn keyword verilogStatement specify specparam strong0 strong1
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43 syn keyword verilogStatement supply0 supply1 table task time tran
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44 syn keyword verilogStatement tranif0 tranif1 tri tri0 tri1 triand
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45 syn keyword verilogStatement trior trireg unsigned use vectored wait
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46 syn keyword verilogStatement wand weak0 weak1 wire wor xnor xor
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47 syn keyword verilogLabel begin end fork join
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48 syn keyword verilogConditional if else case casex casez default endcase
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49 syn keyword verilogRepeat forever repeat while for
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50
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51 syn keyword verilogTodo contained TODO
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52
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53 syn match verilogOperator "[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]"
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54
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316
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55 syn region verilogComment start="/\*" end="\*/" contains=verilogTodo,@Spell
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56 syn match verilogComment "//.*" contains=verilogTodo,@Spell
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7
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57
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58 "syn match verilogGlobal "`[a-zA-Z0-9_]\+\>"
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59 syn match verilogGlobal "`celldefine"
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60 syn match verilogGlobal "`default_nettype"
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61 syn match verilogGlobal "`define"
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62 syn match verilogGlobal "`else"
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63 syn match verilogGlobal "`elsif"
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64 syn match verilogGlobal "`endcelldefine"
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65 syn match verilogGlobal "`endif"
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66 syn match verilogGlobal "`ifdef"
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67 syn match verilogGlobal "`ifndef"
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68 syn match verilogGlobal "`include"
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69 syn match verilogGlobal "`line"
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70 syn match verilogGlobal "`nounconnected_drive"
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71 syn match verilogGlobal "`resetall"
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72 syn match verilogGlobal "`timescale"
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73 syn match verilogGlobal "`unconnected_drive"
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74 syn match verilogGlobal "`undef"
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75 syn match verilogGlobal "$[a-zA-Z0-9_]\+\>"
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76
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77 syn match verilogConstant "\<[A-Z][A-Z0-9_]\+\>"
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78
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1120
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79 syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[bB]\s*[0-1_xXzZ?]\+\>"
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80 syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[oO]\s*[0-7_xXzZ?]\+\>"
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81 syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[dD]\s*[0-9_xXzZ?]\+\>"
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82 syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[hH]\s*[0-9a-fA-F_xXzZ?]\+\>"
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7
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83 syn match verilogNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)\>"
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84
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316
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85 syn region verilogString start=+"+ skip=+\\"+ end=+"+ contains=verilogEscape,@Spell
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7
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86 syn match verilogEscape +\\[nt"\\]+ contained
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87 syn match verilogEscape "\\\o\o\=\o\=" contained
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88
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89 " Directives
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90 syn match verilogDirective "//\s*synopsys\>.*$"
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91 syn region verilogDirective start="/\*\s*synopsys\>" end="\*/"
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92 syn region verilogDirective start="//\s*synopsys dc_script_begin\>" end="//\s*synopsys dc_script_end\>"
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93
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94 syn match verilogDirective "//\s*\$s\>.*$"
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95 syn region verilogDirective start="/\*\s*\$s\>" end="\*/"
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96 syn region verilogDirective start="//\s*\$s dc_script_begin\>" end="//\s*\$s dc_script_end\>"
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97
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98 "Modify the following as needed. The trade-off is performance versus
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99 "functionality.
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316
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100 syn sync minlines=50
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7
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101
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102 " Define the default highlighting.
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103 " For version 5.7 and earlier: only when not done already
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104 " For version 5.8 and later: only when an item doesn't have highlighting yet
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105 if version >= 508 || !exists("did_verilog_syn_inits")
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106 if version < 508
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107 let did_verilog_syn_inits = 1
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108 command -nargs=+ HiLink hi link <args>
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109 else
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110 command -nargs=+ HiLink hi def link <args>
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111 endif
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112
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113 " The default highlighting.
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114 HiLink verilogCharacter Character
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115 HiLink verilogConditional Conditional
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116 HiLink verilogRepeat Repeat
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117 HiLink verilogString String
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118 HiLink verilogTodo Todo
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119 HiLink verilogComment Comment
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120 HiLink verilogConstant Constant
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121 HiLink verilogLabel Label
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122 HiLink verilogNumber Number
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123 HiLink verilogOperator Special
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124 HiLink verilogStatement Statement
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125 HiLink verilogGlobal Define
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126 HiLink verilogDirective SpecialComment
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127 HiLink verilogEscape Special
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128
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129 delcommand HiLink
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130 endif
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131
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132 let b:current_syntax = "verilog"
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133
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134 " vim: ts=8
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